Datasheet

GND

CLKVDD

Internal

Digital In

DACCLKN

OSTRN

S0515-01

DACCLKP

OSTRP

SLEEP

250 Ω

2 kΩ 2 kΩ

DAC3484

www.ti.com

SLAS749C –MARCH 2011–REVISED AUGUST 2012

Table 10. Example Start-Up Sequence Description (continued)

STEP READ/WRITE ADDRESS VALUE DESCRIPTION

FIFO Input Pointer Sync Source = ISTR FIFO Output Pointer Sync Source =

32 Write 0x20 0x2400

OSTR (from PLL N-divider output) Clock Divider Sync Source = OSTR

Provide all the LVDS DATA and DATACLK Provide rising edge FRAMEP/N

33 N/A N/A N/A and rising edge SYNCP/N to sync the FIFO input pointer and PLL N-

dividers.

Read back pll_lfvolt(2:0). If the value is not optimal, adjust pll_vco(5:0) in

34 Read 0x18 N/A

0x1A.

35 Write 0x05 0x0000 Clear all alarms in 0x05.

Read back all alarms in 0x05. Check for PLL lock, FIFO collision, DACCLK-

36 Read 0x05 N/A gone, DATACLK-gone, etc. Fix the error appropriately. Repeat step 34 and

35 as necessary.

Sync all the QMC blocks using sif_sync. These blocks can also be synced

37 Write 0x1F 0x4442

via auto-sync through appropriate register writes.

38 Write 0x00 0xF29B Disable clock divider sync.

39 Write 0x1F 0x4448 Set sif_sync to “0” for the next sif_sync event.

40 Write 0x20 0x0000 Disable FIFO input and output pointer sync.

41 Write 0x18 0x2458 Disable PLL N-dividers sync.

42 N/A N/A N/A Set TXENABLE high. Enable data transmission.

LVPECL INPUTS

Figure 83 shows an equivalent circuit for the DAC input clock (DACCLKP/N) and the output strobe clock

(OSTRP/N).

NOTE: Input common mode level is internally biased

Figure 83. DACCLKP/N and OSTRP/N Equivalent Input Circuit

Product Folder Links: DAC3484