Datasheet

DAC3484
www.ti.com SLAS749C –MARCH 2011–REVISED AUGUST 2012
(b) For Dual Sync Sources Mode, both single pulse or periodic sync signals can be used.
(c) For multi-DAC synchronization in PLL mode, the LVDS SYNCP/N signal is used to sync the PLL N-
divider and can be sourced from either the FPGA/ASIC pattern generator or clock distribution circuit as
long as the t
(SYNC_PLL)
setup and hold timing requirement is met with respect to the reference clock
source at DACCLKP/N pins. The LVDS SYNCP/N signal can be provided at this point.
10. FIFO and clock divider configurations after all the sync signals have provided the initial sync pulses needed
for synchronization:
(a) For Single Sync Source Mode where the clock divider sync source is either FRAMEP/N or SYNCP/N,
clock divider syncing may be disabled after DAC3484 initialization and before the data transmission by
setting clkdiv_sync_ena (config0, bit <2>) to “0”. This is to prevent accidental syncing of the clock divider
or when sending FRAMEP/N or SYNCP/N pulse to other digital blocks.
(b) For Dual Sync Sources Mode, where the clock divider sync source is from the OSTR signal (either from
external OSTRP/N or internal PLL N divider output), the clock divider syncing may be enabled at all time.
(c) Optionally, to prevent accidental syncing of the FIFO and FIFO data formatter when sending the
FRAMEP/N or SYNCP/N pulse to other digital blocks such as NCO, QMC, etc, disable FIFO syncing by
setting syncsel_fifoin(3:0) and syncsel_fifoout(3:0) to “0000” after the FIFO input and output pointers are
initialized. Also Disable the FIFO data formatter by setting syncsel_dataformatter(1:0) to “10” or “11”. If
the FIFO and FIFO data formatter sync remain enabled after initialization, the FRAMEP/N or SYNCP/N
pulse must occur in ways to not disturb the FIFO operation. Refer to the INPUT FIFO section for detail.
(d) Disable PLL N-divider syncing by setting pll_ndivsync_ena (config24, bit<11>) to "0".
11. Enable transmit of data by asserting the TXENABLE pin or set sif_txenable to “1”.
12. At any time, if any of the clocks (i.e DATACLK or DACCLK) is lost or a FIFO collision alarm is detected, a
complete resynchronization of the DAC is necessary. Set TXENABLE low and repeat steps 7 through 11.
Program the FIFO configuration and clock divider configuration per steps 7 and 8 appropriately to accept the
new sync pulse or pulses for the synchronization.
EXAMPLE START-UP ROUTINE
DEVICE CONFIGURATION
f
DATA
= 307.2 MSPS
Interpolation = 4x
Input data = baseband data
f
OUT
= 122.88MHz
PLL = Enabled
Full Mixer = Enabled
Dual Sync Sources Mode
PLL CONFIGURATION
f
REFCLK
= 614.4MHz at the DACCLKP/N LVPECL pins
f
DACCLK
= f
DATA
x Interpolation = 1228.8MHz
f
VCO
= 3 x f
DACCLK
= 3686.4MHz (keep f
VCO
between 3.3GHz to 4GHz)
PFD = f
OSTR
= 38.4MHz
N = 16, M = 32, P = 3, single charge pump
pll_vco(5:0) = “100100” (36)
NCO CONFIGURATION
f
NCO
= 122.88MHz
f
NCO_CLK
= 1228.8MHz
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