Datasheet

DAC3484
SLAS749C –MARCH 2011–REVISED AUGUST 2012 www.ti.com
Parity alarms
• alarm_rparity. Occurs when there is a parity error in the data captured by the rising edge of DATACLKP/N.
The PARITYP/N input is the parity bit (word-by-word parity test).
• alarm_fparity. Occurs when there is a parity error in the data captured by the falling edge of DATACLKP/N.
The PARITYP/N input is the parity bit (word-by-word parity test).
• alarm_frame_parity_err. Occurs when there is a frame parity error when using the FRAME as the parity bit
(block parity test).
To prevent unexpected DAC outputs from propagating into the transmit channel chain, the clock and alarm_
fifo_collision alarms can be set in config2 to shut-off the DAC output automatically regardless of the state of
TXENABLE or sif_txenable.
Alarm monitoring is implemented as follows:
• Power up the device using the recommended power-up sequence.
• Clear all the alarms in config5 by setting them to 0.
• Unmask those alarms that will generate a hardware interrupt through the ALARM pin in config7.
• Enable automatic DAC shut-off in register config2 if required.
• In the case of an alarm event, the ALARM pin will trigger. If automatic DAC shut-off has been enabled the
DAC outputs will be disabled.
• Read registers config5 to determine which alarm triggered the ALARM pin.
• Correct the error condition and re-synchronize the FIFO.
• Clear the alarms in config5.
• Re-read config5 to ensure the alarm event has been corrected.
• Keep clearing and reading config5 until no error is reported.
POWER-UP SEQUENCE
The following startup sequence is recommended to power-up the DAC3484:
1. Set TXENABLE low
2. Supply all 1.2V voltages (DACVDD, DIGVDD, CLKVDD, and VFUSE) and all 3.3V voltages (AVDD, IOVDD,
and PLLAVDD). The 1.2V and 3.3V supplies can be powered up simultaneously or in any order. There are
no specific requirements on the ramp rate for the supplies.
3. Provide all LVPECL inputs: DACCLKP/N and the optional OSTRP/N. These inputs can also be provided after
the SIF register programming.
4. Toggle the RESETB pin for a minimum 25 ns active low pulse width.
5. Program the SIF registers.
6. Program fuse_sleep (config27, bit<11>) to put the internal fuses to sleep. To enable dual channel mode, set
Config1, bit <8> to "0" and Config16, bit<13:12> to "11". This dual channel mode is functionally equivalent to
the dual channel DAC3482 (channels B and C active). See the DAC3482 SLAS748 datasheet for details.
7. FIFO configuration needed for synchronization:
(a) Program syncsel_fifoin(3:0) (config32, bits<15:12>) to select the FIFO input pointer sync source.
(b) Program syncsel_fifoout(3:0) (config32, bits<11:8>) to select the FIFO output pointer sync source.
(c) Program syncsel_dataformatter(1:0) (config31, bits<3:2>) to select the FIFO Data Formatter sync source.
8. Clock divider configuration needed for synchronization:
(a) Program clkdiv_sync_sel (config32, bit<0>) to select the clock divider sync source.
(b) Program clkdiv_sync_ena (config0, bit<2>) to "1" to enable clock divider sync.
(c) For multi-DAC synchronization in PLL mode, program pll_ndivsync_ena (config24, bit<11>) to “1” to
synchronize the PLL N-divider.
9. Provide all LVDS inputs (D[15:0]P/N, DATACLKP/N, FRAMEP/N, SYNCP/N, and PARITYP/N)
simultaneously. Synchronize the FIFO and clock divider by providing the pulse or periodic signals needed.
(a) For Single Sync Source Mode where either FRAMEP/N or SYNCP/N is used to sync the FIFO, a single
rising edge for FIFO, FIFO data formatter, and clock divider sync is recommended. Periodic sync signal
is not recommended due to the non-deterministic latency of the sync signal through the clock domain
transfer.
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