Datasheet

D[15:0]
PARITY
DATACLK
alarm_rparity
alarm_fparity
B0458-01
Parity Block
oddeven_parity
DAC3484
SLAS749C –MARCH 2011–REVISED AUGUST 2012 www.ti.com
PARITY CHECK TEST
The DAC3484 has a parity check test that enables continuous validity monitoring of the data received by the
DAC. Parity check testing in combination with the data pattern checker offer an excellent solution for detecting
board assembly issues due to missing pad connections.
For the parity check test, an extra parity bit is added to the data bits to ensure that the total number of set bits
(bits with value 1) is even or odd. This simple scheme is used to detect single or any other odd number of data
transfer errors. Parity testing is implemented in the DAC3484 in two ways: word-by-word parity and block parity.
WORD-BY-WORD PARITY
Word-by-word parity is the easiest mode to implement. In this mode the additional parity bit is sourced to the
parity input (PARITYP/N) for each data word transfer into the D[15:0]P/N inputs. This mode is enabled by setting
the word_parity_ena bit. The input parity value is defined to be the total number of logic 1s on the 17-bit data
bus, the D[15:0]P/N inputs and the PARITYP/N input. This value, the total number of logic 1s, must match the
parity test selected in the oddeven_parity bit in register config1.
For example, if the oddeven_parity bit is set to “1” for odd parity, then the number of 1s on the 17-bit data bus
should be odd. The DAC will check the data transfer through the parity input. If the data received has odd
number of 1s, then the parity is correct. If the data received has even number of 1s, then the parity is incorrect.
The corresponding alarm for parity error will be set accordingly.
Figure 81 shows the simple XOR structure used to check word parity. Parity is tested independently for data
captured on both rising and falling edges of DATACLK (alarm_rparity and alarm_fparity, respectively). Testing on
both edges helps in determining a possible setup/hold issue. Both alarms are captured individually in register
config5.
Figure 81. DAC3484 Word-by-Word Parity Check
BLOCK PARITY
The block parity method uses the FRAME signal to determine the boundaries of the data block to compute parity.
This mode is enabled by setting the frame_parity_ena bit in register config1.
A low-to-high transition of FRAME captured with the DATACLK rising edge determines the end point of the parity
block and the beginning of the next one. In this method the parity bit of the completed block corresponds to the
FRAME value captured on the DATACLK falling edge right after the STOP/START point.
The input parity value is defined to be the total number of logic 1s in the data block. A logic HIGH captured on
the falling edge of DATACLK indicates odd parity or odd number of logic 1s, while a logic LOW indicates even
parity or even number of logic 1s. If the expected parity does not match the number of logic 1s in the received
data, then alarm_frame_parity in register config5 will be set to “1”. The main advantage of the block parity mode
is that there is no need for an additional parity LVDS input.
Since the FRAME signal is used for parity testing in addition to FIFO syncing and frame boundary assignment it
is mandatory to take some extra steps to avoid device malfunction. If FRAME is used to reset the FIFO pointers
continuosly, the block size must be a multiple of 8 samples (each sample corresponding to 16-bits A, B, C and D
data). In addition since FRAME is used to establish the frame boundary, the parity block must be aligned with the
data frame boundaries.
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