Datasheet

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DAC3484

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SLAS749C –MARCH 2011–REVISED AUGUST 2012

PIN FUNCTIONS

I/O DESCRIPTION

NAME NO.

D10, E11,

F11, G11,

AVDD I Analog supply voltage. (3.3 V)

H11, J11,

K11, L10

CMOS output for ALARM condition. The ALARM output functionality is defined through the config7

ALARM N12 O register. Default polarity is active low, but can be changed to active high via config0 alarm_out_pol

control bit.

Full-scale output current bias. For 30mA full-scale output current, connect 1.28kΩ to ground. Change

BIASJ H12 O

the full-scale output current through coarse_dac(3:0) in config3, bit<15:12>

Internal clock buffer supply voltage. (1.2 V)

CLKVDD C12 I

It is recommended to isolate this supply from DIGVDD and DACVDD.

LVDS positive input data bits 0 through 15. Internal 100 Ω termination resistor. Data format relative to

N4, N3, N2,

DATACLKP/N clock is Double Data Rate (DDR).

N1, M2, L2,

K2, J2, F2,

D15P is most significant data bit (MSB)

D[15..0]P I

E2, D2, C2,

D0P is least significant data bit (LSB)

A1, A2, A3,

The order of the bus can be reversed via config2 revbus bit.

P4, P3, P2,

P1, M1, L1,

K1, J1, F1,

D[15..0]N I LVDS negative input data bits 0 through 15. (See D[15:0]P description above)

E1, D1, C1,

B1, B2, B3,

DACCLKP A12 I Positive external LVPECL clock input for DAC core with a self-bias.

DACCLKN A11 I Complementary external LVPECL clock input for DAC core. (see the DACCLKP description)

D9, E9, E10,

F10, G10, DAC core supply voltage. (1.2 V). It is recommended to isolate this supply from CLKVDD and

DACVDD I

H10, J10, K9, DIGVDD.

K10, L9

LVDS positive input data clock. Internal 100 Ω termination resistor. Input data D[15:0]P/N is latched

DATACLKP G2 I

on both edges of DATACLKP/N (Double Data Rate).

DATACLKN G1 I LVDS negative input data clock. (See DATACLKP description)

E5, E6, E7,

DIGVDD F5, J5, K5, I Digital supply voltage. (1.2 V). It is recommended to isolate this supply from CLKVDD and DACVDD.

K6, K7

Used as external reference input when internal reference is disabled through config27 extref_ena =

EXTIO G12 I/O ‘1’. Used as internal reference output when config27 extref_ena = ‘0’ (default). Requires a 0.1 μF

decoupling capacitor to AGND when used as reference output.

LVDS frame indicator positive input. Internal 100 Ω termination resistor.

The main functions of this input are to reset the FIFO pointer or to be used as a syncing source.

These two functions are captured with the rising edge of DATACLKP/N. The signal captured by the

FRAMEP H2 I

falling edge of DATACLKP/N can be used as a block parity bit. The FRAMEP/N signal should be

edge-aligned with D[15:0]P/N.

Additionally it is used to indicate the beginning of the frame.

FRAMEN H1 I LVDS frame indicator negative input. (See the FRAMEP description)