Datasheet

Clock Generator
DATACLKP/N
FRAMEP/N
FPGA
D[15:0]P/N
D[15:0]P/N
DATACLKP/N
FRAMEP/N
DACCLKP/N
B0456-03
LVPECL Outputs
LVDS Interface
LVPECL Outputs
DACCLKP/N
PLL/
DLL
DAC3484 DAC1
Delay 1
Delay 2
DAC3484 DAC2
0 to 2 DAC Clock Cycles
Variable delays due to variations in the FPGA(s) output
paths or board level wiring or temperature/voltage deltas
DAC3484
www.ti.com SLAS749C –MARCH 2011–REVISED AUGUST 2012
Figure 63. Multi-Device Operation in Single Sync Source Mode
FIR FILTERS
Figure 64 through Figure 67 show the magnitude spectrum response for the FIR0, FIR1, FIR2 and FIR3
interpolating filters where f
IN
is the input data rate to the FIR filter. Figure 68 to Figure 71 show the composite
filter response for 2x, 4x, 8x and 16x interpolation. The transition band for all interpolation settings is from 0.4 to
0.6 x f
DATA
(the input data rate to the device) with <0.001dB of pass-band ripple and >90 dB stop-band
attenuation.
The DAC3484 also has a 9-tap inverse sinc filter (FIR4) that runs at the DAC update rate (f
DAC
) that can be used
to flatten the frequency response of the sample-and-hold output. The DAC sample-and-hold output sets the
output current and holds it constant for one DAC clock cycle until the next sample, resulting in the well-known
sin(x)/x or sinc(x) frequency response (Figure 72, red line). The inverse sinc filter response (Figure 72, blue line)
has the opposite frequency response from 0 to 0.4 x Fdac, resulting in the combined response (Figure 72, green
line). Between 0 to 0.4 x f
DAC
, the inverse sinc filter compensates the sample-and-hold roll-off with less than 0.03
dB error.
The inverse sinc filter has a gain >1 at all frequencies. Therefore, the signal input to FIR4 must be reduced from
full scale to prevent saturation in the filter. The amount of back-off required depends on the signal frequency, and
is set such that at the signal frequencies the combination of the input signal and filter response is less than 1 (0
dB). For example, if the signal input to FIR4 is at 0.25 x f
DAC
, the response of FIR4 is 0.9 dB, and the signal must
be backed off from full scale by 0.9 dB to avoid saturation. The gain function in the QMC blocks can be used to
reduce the amplitude of the input signal. The advantage of FIR4 having a positive gain at all frequencies is that
the user is then able to optimize the back-off of the signal based on its frequency.
The filter taps for all digital filters are listed in Table 4. Note that the loss of signal amplitude may result in lower
SNR due to decrease in signal amplitude.
SPACER
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