Datasheet

T0526-03

DACCLKP/N(2)

DACCLKP/N(1)

•

OSTRP/N(2)

OSTRP/N(1)

LVPECL Pairs (DAC3484 2)

LVPECL Pairs (DAC3484 1)

S(OSTR)

SKEW ~ 0

H(OSTR)

DAC3484

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SLAS749C –MARCH 2011–REVISED AUGUST 2012

For correct operation both OSTR and DACCLK must be generated from the same clock domain. The OSTR

signal is sampled by DACCLK and must satisfy the timing requirements in the specifications table. If the clock

generator does not have the ability to delay the DACCLK to meet the OSTR timing requirement, the polarity of

the DACCLK outputs can be swapped with respect to the OSTR ones to create 180 degree phase delay of the

DACCLK. This may help establish proper setup and hold time requirement of the OSTR signal.

Careful board layout planning must be done to ensure that the DACCLK and OSTR signals are distributed from

device to device with the lowest skew possible as this will affect the synchronization process. In order to

minimize the skew across devices it is recommended to use the same clock distribution device to provide the

DACCLK and OSTR signals to all the DAC devices in the system.

Figure 61. Timing Diagram for LVPECL Synchronization Signals

The following steps are required to ensure the devices are fully synchronized. The procedure assumes all the

DAC3484 devices have a DACCLK and OSTR signal and must be carried out on each device.

1. Start-up the device as described in the power-up sequence. Set the DAC3484 in Dual Sync Sources mode

and select OSTR as the clock divider sync source (clkdiv_sync_sel in register config32).

2. Sync the clock divider and FIFO pointers.

3. Verify there are no FIFO alarms either through register config5 or through the ALARM pin.

4. Disable clock divider sync by setting clkdiv_sync_ena to "0" in register config0.

After these steps all the DAC3484 outputs will be synchronized.

MULTI-DEVICE SYNCHRONIZATION: PLL ENABLED WITH DUAL SYNC SOURCES MODE

The DAC3484 allows exact phase alignment between multiple devices even when operating with the internal PLL

clock multiplier. In PLL clock mode, the PLL generates the DAC clock and an internal OSTR signal from the

reference clock applied to the DACCLK inputs so there is no need to supply an additional LVPECL OSTR signal.

For this method to operate properly the SYNC signal should be set to reset the PLL N dividers to a known state

by setting pll_ndivsync_ena in register config24 to “1”. The SYNC signal resets the PLL N dividers with a rising

edge, and the timing relationship t

s(SYNC_PLL)

and t

h(SYNC_PLL)

are relative to the reference clock presented on the

DACCLK pin.

Product Folder Links: DAC3484