Datasheet

Clock Generator
DATACLKP/N
FRAMEP/N
FPGA
D[15:0]P/N
D[15:0]P/N
DATACLKP/N
FRAMEP/N
DACCLKP/N
B0454-03
LVPECL Outputs
LVDS Interface
OSTRP/N
LVPECL Outputs
DACCLKP/N
OSTRP/N
PLL/
DLL
DAC3484 DAC1
Delay 1
Delay 2
Outputs are
Phase Aligned
DAC3484 DAC2
Variable delays due to variations in the FPGA(s) output
paths or board level wiring or temperature/voltage deltas
LPF
S0514-01
R = 1 kΩ
C1 = 100 nF
C2 = 1 nF
DAC3484
SLAS749C –MARCH 2011–REVISED AUGUST 2012 www.ti.com
Figure 59. Recommended External Loop Filter
The PLL generates an internal OSTR signal and does not require the external LVPECL OSTR signal. The OSTR
signal is buffered from the N-divider output in the PLL block, and the frequency of the signal is the same as the
PFD frequency. Therefore, using PLL with Dual Sync Sources mode would require the PFD frequency to be the
pre-defined OSTR frequency. This will allow the FIFO to be synced correctly by the internal OSTR.
MULTI-DEVICE SYNCHRONIZATION
In various applications, such as multi antenna systems where the various transmit channels information is
correlated, it is required that multiple DAC devices are completely synchronized such that their outputs are phase
aligned. The DAC3484 architecture supports this mode of operation.
MULTI-DEVICE SYNCHRONIZATION: PLL BYPASSED WITH DUAL SYNC SOURCES MODE
For single or multi-device synchronization it is important that delay differences in the data are absorbed by the
device so that latency through the device remains the same. Furthermore, to guarantee that the outputs from
each DAC are phase aligned it is necessary that data is read from the FIFO of each device simultaneously. In
the DAC3484 this is accomplished by operating the multiple devices in Dual Sync Sources mode. In this mode
the additional OSTR signal is required by each DAC3484 to be synchronized.
Data into the device is input as LVDS signals from one or multiple baseband ASICs or FPGAs. Data into the
multiple DAC devices can experience different delays due to variations in the digital source output paths or board
level wiring. These different delays can be effectively absorbed by the DAC3484 FIFO so that all outputs are
phase aligned correctly.
Figure 60. SynchronizationSystem in Dual Sync Sources Mode with PLL Bypassed
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