Datasheet
3300
3400
3500
3600
3700
3800
3900
4000
0 8 16
24
32 40 48 56 64
Coarse-Tuning Bits
VCO Frequency (MHz)
( )
VCO Frequency MHz 3253
Coarse-Tuning Bits
11.6
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@
DAC3484
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SLAS749C –MARCH 2011–REVISED AUGUST 2012
Figure 58. Typical PLL/VCO Lock Range vs Coarse Tuning Bits
Common wireless infrastructure frequencies (614.4MHz, 737.28MHz, 1.2288GHz, etc.) are generated from this
VCO frequency in conjunction with the pre-scaler setting as shown in Table 5.
Table 5. VCO Operation
VCO Frequency (MHz) Pre-Scale Divider Desired DACCLK (MHz) pll_p(2:0)
3440.64 7 491.52 111
3686.4 6 614.4 110
3686.4 5 737.28 101
3686.4 3 1228.8 011
The M divider is used to determine the phase-frequency-detector (PFD) and charge-pump (CP) frequency.
Table 6. PFD and CP Operation
DACCLK Frequency
M Divider PDF Update Rate (MHz) pll_m(7:0)
(MHz)
491.52 4 122.88 00000100
491.52 8 61.44 00001000
491.52 16 30.72 00010000
491.52 32 15.36 00100000
The N divider in the loop allows the PFD to operate at a lower frequency than the reference clock. Both M and N
dividers can keep the PFD frequency below 155 MHz for peak operation.
The overall divide ratio inside the loop is the product of the Pre-Scale and M dividers (P * M) and the following
guidelines should be followed:
• The overall divide ratio range is from 24 to 480
• When the overall divide ratio is less than 120, the internal loop filter can guarantee a stable loop
• When the overall divide ratio is greater than 120, an external loop filter or double charge pump is required to
ensure loop stability
The single- and double-charge-pump current option are selected by setting pll_cp in register config24 to 01 and
11, respectively. When using the double-charge-pump setting, an exteranl loop filter is not required. If an external
filter is required, the following filter should be connected to the LPF pin (A1):
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