Datasheet
SYNCP
DACCLKP
N
Divider
PFD
and
CP
SYNCN
DACCLKN
External Loop
Filter
Internal Loop
Filter
VCO
B0453-01
Prescaler
M
Divider
DACCLK
REFCLK
SYNC_PLL
OSTR (Internally Generated)
Note:
The PLL generates internal OSTR signal. In this mode
external LVPECL OSTR signal is not required.
If the DAC is configured with PLL enabled with Dual Sync
Sources mode, then the PFD frequency has to be the pre-
defined OSTR frequency.
DAC3484
SLAS749C –MARCH 2011–REVISED AUGUST 2012
www.ti.com
PLL BYPASS MODE
In PLL bypass mode a very high quality clock is sourced to the DACCLK inputs. This clock is used to directly
clock the DAC3484 DAC sample rate clock. This mode gives the device best performance and is recommended
for extremely demanding applications.
The bypass mode is selected by setting the following:
1. pll_ena bit in register config24 to “0” to bypass the PLL circuitry.
2. pll_sleep bit in register config26 to “1” to put the PLL and VCO into sleep mode.
PLL MODE
In this mode the clock at the DACCLK input functions as a reference clock source to the on-chip PLL. The on-
chip PLL will then multiply this reference clock to supply a higher frequency DAC sample rate clock. Figure 57
shows the block diagram of the PLL circuit.
Figure 57. PLL Block Diagram
The DAC3484 PLL mode is selected by setting the following:
1. pll_ena bit in register config24 to “1” to route to the PLL clock path.
2. pll_sleep bit in register config26 to “0” to enable the PLL and VCO.
The output frequency of the VCO is designed to be the in the range from 3.3GHz to 4.0GHz. The prescaler
value, pll_p(2:0) in register config24, should be chosen such that the product of the prescaler value and DAC
sample rate clock is within the VCO range. To maintain optimal PLL loop, the coarse tune bits, pll_vco(5:0) in
register config26, can adjust the center frequency of the VCO towards the product of the prescaler value and
DAC sample rate clock. Figure 58 shows a typical relationship between coarse tune bits and VCO center
frequency.
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