Datasheet

DACCLK
pll_ena
Clock Distribution
to Digital
VCO/
Dividers
PLL
16-Bit
DACI
16-Bit
DACQ
B0452-01
DAC3484
www.ti.com
SLAS749C MARCH 2011REVISED AUGUST 2012
Table 4. FIFO Operation Modes
config0 and config32 FIFO Bits
FIFO Mode syncsel_fifoout
fifo_ena
Bit 3: sif_sync Bit 2: OSTR Bit 1: FRAME Bit 0: SYNC
Dual Sync Sources 1 0 1 0 0
Single Sync 1 or 0 Depends on the sync 1 or 0 Depends on the
1 0 0
Source source sync source
Bypass 0 X X X X
DUAL SYNC SOURCES MODE
This is the recommended mode of operation for those applications that require precise control of the output
timing. In Dual Sync Sources mode, the FIFO write and read pointers are reset independently. The FIFO write
pointer is reset using the LVDS FRAME or SYNC signal, and the FIFO read pointer is reset using the LVPECL
OSTR signal. This allows LVPECL OSTR signal to control the phase of the output for either a single chip or
multiple chips. Multiple devices can be fully synchronized in this mode.
SINGLE SYNC SOURCE MODE
In Single Sync Source mode, the FIFO write and read pointers are reset from the same source, either LVDS
FRAME or LVDS SYNC signal. This mode has a possibility of up to 2 DAC clocks offset between the multiple
DAC outputs. Applications requiring exact output timing control will need Dual Sync Sources mode instead of
Single Sync Source Mode. A rising edge for FIFO and clock divider sync is recommended. Periodic sync signal
is not recommended due to non-deterministic latency of the sync signal through the clock domain transfer.
BYPASS MODE
In FIFO bypass mode, the FIFO block is not used. As a result the input data is handed off from the DATACLK to
the DACCLK domain without any compensation. In this mode the relationship between DATACLK and DACCLK
is critical and used as a synchronizing mechanism for the internal logic. Due to the this constraint this mode is
not recommended. In bypass mode the pointers have no effect on the data path or handoff.
CLOCKING MODES
The DAC3484 has a dual clock setup in which a DAC clock signal is used to clock the DAC cores and internal
digital logic and a separate DATA clock is used to clock the input LVDS receivers and FIFO input. The DAC3484
DAC clock signal can be sourced directly or generated through an on-chip low-jitter phase-locked loop (PLL).
In those applications requiring extremely low noise it is recommended to bypass the PLL and source the DAC
clock directly from a high-quality external clock to the DACCLK input. In most applications system clocking can
be simplified by using the on-chip PLL to generate the DAC core clock while still satisfying performance
requirements. In this case the DACCLK pins are used as the reference frequency input to the PLL.
Figure 56. Top Level Clock Diagram
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