Datasheet

T0535-01
Resets Write Pointer to Position 0
Resets Read Pointer to Position
Set by fifo_offset (4 by Default)
DATACLKP/N
(DDR)
FRAMEP/N
SYNCP/N
DACCLKP/N
2x Interpolation
OSTRP/N
(optionally internal
sync from Write Reset)
D[15:0]P/N
LVDS Pairs (Data Source)
LVPECL Pairs (Clock Source)
t
S(OSTR)
t
H(DATA)
t
H(DATA)
t
H(DATA)
t
H(OSTR)
t
S(DATA)
t
S(DATA)
t
S(DATA)
DAC3484
SLAS749C –MARCH 2011–REVISED AUGUST 2012 www.ti.com
To alleviate this, the device offers the alternative of resetting the FIFO read pointer independently of the write
pointer by using the OSTR signal. The OSTR signal is sampled by DACCLK and must satisfy the timing
requirements in the specifications table. In order to minimize the skew it is recommended to use the same clock
distribution device such as Texas Instruments CDCE62005 to provide the DACCLK and OSTR signals to all the
DAC3484 devices in the system. Swapping the polarity of the DACCLK outputs with respect to the OSTR ones
establishes proper phase relationship.
The FIFO pointers reset procedure can be done periodically or only once during initialization as the pointers
automatically return to the initial position when the FIFO has been filled. To reset the FIFO periodically, it is
necessary to have the FRAME, SYNC, and OSTR signals to repeat at multiples of 8 FIFO samples. To disable
FIFO reset, set syncsel_fifoin(3:0) and syncsel_fifoout(3:0) to “0000”.
The frequency limitation for FRAME and SYNC signals are the following:
f
sync
= f
DATACLK
/(n x 16) where n = 1, 2, … for Word-Wide and Byte-Wide Mode
The frequency limitation for the OSTR signal is the following:
f
OSTR
= f
DAC
/(n x interpolation x 8) where n = 1, 2, …
The frequencies above are at maximum when n = 1. This is when the FRAME, SYNC, or OSTR have a rising
edge transition every 8 FIFO samples. The occurrence can be made less frequent by setting n > 1, for example,
every n × 8 FIFO samples.
Figure 55. FIFO Write and Read Descriptions
FIFO MODES OF OPERATION
The DAC3484 input FIFO can be completely bypassed through registers config0 and config32. The register
configuration for each mode is described in Table 4.
Register Control Bits
config0 fifo_ena
config32 syncsel_fifoout(3:0)
50 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links: DAC3484