Datasheet

FIFO Reset
D[15:0]
FIFO A Output
FIFO B Output
Clock Handoff
64-Bit
64-Bit
A-Data, 16-Bit
16-Bit
16-Bit
B-Data, 16-Bit
C-Data, 16-Bit
D-Data, 16-Bit
16-Bit
16-Bit
16-Bit
16-Bit
Write Pointer Reset
Read Pointer Reset
FIFO C Output
FIFO D Output
OSTR
B0465-01
syncsel_fifoin
syncsel_fifoout
S M
fifo_offset(2:0)
FRAME/
SYNC
Input Side
Clocked by DATACLK
x2
Two Cycles to Capture 64 Bits
(16 for Each Channel)
0 ... 7
Write Pointer
0 ... 7
Read Pointer
S (Single Sync Source Mode): Reset handoff from
input side to output side
M (Dual Sync Sources Mode): OSTR resets read
pointer. Allows Multi-DAC synchronization
Initial
Position
Initial
Position
FIFO:
4 x 16-Bits Wide
8-Samples deep
Output Side
Clocked by FIFO Out Clock
( )DACCLK/Interpolation Factor
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Sample 0
A [15:0], B [15:0], C
0 0 0 0
[15:0], D [15:0]
Sample 0
A [15:0], B [15:0], C
1 1 1 1
[15:0], D [15:0]
Sample 0
A [15:0], B [15:0], C
2 2 2 2
[15:0], D [15:0]
Sample 0
A [15:0], B [15:0], C
3 3 3 3
[15:0], D [15:0]
Sample 0
A [15:0], B [15:0], C
4 4 4 4
[15:0], D [15:0]
Sample 0
A [15:0], B [15:0], C
5 5 5 5
[15:0], D [15:0]
Sample 0
A [15:0], B [15:0], C
6 6 6 6
[15:0], D [15:0]
Sample 0
A [15:0], B [15:0], C
7 7 7 7
[15:0], D [15:0]
Frame Align
DAC3484
www.ti.com SLAS749C –MARCH 2011–REVISED AUGUST 2012
Figure 54. DAC3484 FIFO Block Diagram
Data is written to the device 16-bits at a time on the rising and falling edges of DATACLK. In order to form a
complete 64-bit wide sample (16-bit A-data, 16-bit B-data, 16-bit C-data, and 16-bit D-data) two DATACLK
periods are required. Each 64-bit wide sample is written into the FIFO at the address indicated by the write
pointer. Similarly, data from the FIFO is read by the FIFO Out Clock 64-bits at a time from the address indicated
by the read pointer. The FIFO Out Clock is generated internally from the DACCLK signal and its rate is equal to
DACCLK/Interpolation. Each time a FIFO write or FIFO read is done the corresponding pointer moves to the next
address.
The reset position for the FIFO read and write pointers is set by default to addresses 0 and 4 as shown in
Figure 54. This offset gives optimal margin within the FIFO. The default read pointer location can be set to
another value using fifo_offset(2:0) in register config9 (address 4 by default). Under normal conditions data is
written-to and read-from the FIFO at the same rate and consequently the write and read pointer gap remains
constant. If the FIFO write and read rates are different, the corresponding pointers will be cycling at different
speeds which could result in pointer collision. Under this condition the FIFO attempts to read and write data from
the same address at the same time which will result in errors and thus must be avoided.
The write pointer sync source is selected by syncsel_fifoin(3:0) in register config32. In most applications either
FRAME or SYNC are used to reset the write pointer. Unlike DATA, the sync signal is latched only on the rising
edges of DATACLK. A rising edge on the sync signal source causes the pointer to return to its original position.
Similarly, the read pointer sync source is selected by syncsel_fifoout(3:0). The write pointer sync source can be
set to reset the read pointer as well. In this case, FIFO Out clock will recapture the write pointer sync signal to
reset the read pointer. This clock domain transfer (DATACLK to FIFO Out Clock) results in phase ambiguity of
the reset signal. This limits the precise control of the output timing and makes full synchronization of multiple
devices difficult.
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