Datasheet

D[7:0]P/N
D[15:8]P/N
FRAMEP/N
SAMPLE 0 SAMPLE 1
SYNCP/N
T0534-01
t
(FRAME_SYNC)
t
(FRAME_SYNC)
DATACLKP/N (DDR)
C
[15:8]
0
A
[15:8]
0
D
[15:8]
0
B
[15:8]
0
C
[15:8]
1
A
[15:8]
1
D
[15:8]
1
B
[15:8]
1
C
[7:0]
0
A
[7:0]
0
D
[7:0]
0
B
[7:0]
0
C
[7:0]
1
A
[7:0]
1
D
[7:0]
1
B
[7:0]
1
Optional
Parity Bit
Sync
Option #1
Sync
Option #2
DAC3484
SLAS749C –MARCH 2011–REVISED AUGUST 2012 www.ti.com
BYTE-WIDE FORMAT
The dual-bus, 8-bit interface is selected by setting 16bit_in to “0” in the config2 register. In this mode the 16-bit
data for channels A and B is interleaved in the form A
0
[15:8], A
0
[7:0], B
0
[15:8], B
0
[7:0], A
1
[15:8]… into the
D[15:8]P/N LVDS inputs. Similarly data for channels C and D is interleaved into the D[7:0]P/N LVDS inputs. Data
into the DAC3484 is formatted according to the diagram shown in Figure 53 where index 0 is the data LSB and
index 15 is the data MSB.
Figure 53. Byte-wide Data Transmission Format
INPUT FIFO
The DAC3484 includes a 4-channel, 16-bits wide and 8-samples deep input FIFO which acts as an elastic buffer.
The purpose of the FIFO is to absorb any timing variations between the input data and the internal DAC data
rate clock such as the ones resulting from clock-to-data variations from the data source.
Figure 54 shows a simplified block diagram of the FIFO.
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