Datasheet

D[15:0]P/N
FRAMEP/N
SAMPLE 0 SAMPLE 1
SYNCP/N
T0533-01
t
(FRAME_SYNC)
t
(FRAME_SYNC)
DATACLKP/N (DDR)
A
[15:0]
0
C
[15:0]
0
A
[15:0]
1
C
[15:0]
1
B
[15:0]
0
D
[15:0]
0
B
[15:0]
1
D
[15:0]
1
Optional
Parity Bit
Sync
Option #1
Sync
Option #2
DAC3484
www.ti.com SLAS749C –MARCH 2011–REVISED AUGUST 2012
DATA INTERFACE
The DAC3484 has a 16-bit LVDS bus that accepts quad, 16-bit data either in word-wide or dual byte-wide
formats. The quad, 16-bit data can be input to the device using either a single-bus, 16-bit interface or a dual-bus,
8-bit interface. The selection between the two modes is done through 16bit_in in the config2 register. The LVDS
bus inputs in each mode are shown in Table 3.
Table 3. LVDS Bus Input Assignment
Input Mode Pins
Word-wide D[15..0] → Data for paths A, B, C
and D
Byte-wide D[15..8] → Data for paths A and B
D[7..0] → Data for paths C and D
Data is sampled by the LVDS double data rate (DDR) clock DATACLK. Setup and hold requirements must be
met for proper sampling.
For both input bus modes, a sync signal, either FRAME or SYNC, can sync the FIFO read and/or write pointers.
In byte-wide mode the sync source is needed to establish the correct sample boundaries.
The sync signal, either FRAME or SYNC, can be either a pulse or a periodic signal where the sync period
corresponds to multiples of 8 samples. FRAME or SYNC is sampled by a rising edge in DATACLK. The pulse-
width t
(FRAME_SYNC)
needs to be at least equal to 1/2 of the DATACLK period.
For both input bus mode, the value in FRAME sampled by the next falling edge in DATACLK can be used as a
block parity value. This feature is enabled by setting frame_parity_ena in register config1 to “1”. Refer to “Parity
Check Test” section for more detail
WORD-WIDE FORMAT
The single-bus, 16-bit interface is selected by setting 16bit_in to “1” in the config2 register. In this mode the 16-bit
data for channels A, B, C and D is input word-wide interleaved in the form A
0
, B
0
, C
0
, D
0
, A1… into the
D[15:0]P/N LVDS bus. Data into the DAC3484 is formatted according to the diagram shown in Figure 52 where
index 0 is the data LSB and index 15 is the data MSB.
Figure 52. Word-wide Data Transmission Format
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