Datasheet

DAC3484
www.ti.com SLAS749C –MARCH 2011–REVISED AUGUST 2012
Register name: config20 – Address: 0x14, Default: 0x0000
Register
Default
Address Bit Name Function
Value
Name
config20 0x14 15:0 phase_ addAB(15:0) The phase_addAB(15:0) value is used to determine the NCO frequency. The two’s 0x0000
complement formatted value can be positive or negative. Each LSB represents
Fs/(2^32) frequency step.
Register name: config21 – Address: 0x15, Default: 0x0000
Register
Default
Address Bit Name Function
Value
Name
config21 0x15 15:0 phase_ addAB(31:16) See config20 above. 0x0000
Register name: config22 – Address: 0x16, Default: 0x0000
Register
Default
Address Bit Name Function
Value
Name
config22 0x16 15:0 phase_ addCD(15:0) The phase_addCD(15:0) value is used to determine the NCO frequency. The two’s 0x0000
complement formatted value can be positive or negative. Each LSB represents
Fs/(2^32) frequency step.
Register name: config23 – Address: 0x17, Default: 0x0000
Register
Default
Address Bit Name Function
Value
Name
config23 0x17 15:0 phase_ addCD(31:16) See config22 above. 0x0000
Register name: config24 – Address: 0x18, Default: NA
Register
Default
Address Bit Name Function
Value
Name
config24 0x18 15:13 Reserved Reserved for factory use. 001
12 pll_reset When set, the PLL loop filter (LPF) is pulled down to 0V. Toggle from ‘1’ to ‘0’ to 0
restart the PLL if an over-speed lock-up occurs. Over-speed can happen when the
process is fast, the supplies are higher than nominal, etc. resulting in the feedback
dividers missing a clock.
11 pll_ndivsync_ena When set, the LVDS SYNC input is used to sync the PLL N dividers. 1
10 pll_ena When set, the PLL is enabled. When cleared, the PLL is bypassed. 0
9:8 Reserved Reserved for factory use. 00
7:6 pll_cp(1:0) PLL pump charge select 00
MM 00: No charge pump
MM 01: Single pump charge
MM 10: Not used
MM 11: Dual pump charge
5:3 pll_p(2:0) PLL pre-scaler dividing module control. 001
MM 010: 2
MM 011: 3
MM 100: 4
MM 101: 5
MM 110: 6
MM 111: 7
MM 000: 8
2:0 pll_lfvolt(2:0) PLL loop filter voltage. This three bit read-only indicator has step size of 0.4125V. NA
The entire range covers from 0V to 3.3V. The optimal lock range of the PLL will be
from 010 to 101 (i.e. 0.825V to 2.063V). Adjust pll_vco(5:0) for optimal lock range.
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