Datasheet

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EXTIO
FS
BIAS
V
I 2 coarse _ dac 1
R
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DAC3484
SLAS749C –MARCH 2011–REVISED AUGUST 2012 www.ti.com
Register name: config2 – Address: 0x02, Default: 0x7000
Register Default
Address Bit Name Function
Name Value
config2 0x02 15 16bit_in When set, the input interface is set to word-wide mode. 0
When cleared, the input interface is set to byte-wide mode.
14 dacclkgone_ena When set, the DACCLK-gone signal from the clock monitor circuit can 1
be used to shut off the DAC outputs. The corresponding alarms,
alarm_dacclk_gone and alarm_output_gone, must not be masked
(i.e.Config7, bit <10> and bit <8> must set to "0").
13 dataclkgone_ena When set, the DATACLK-gone signal from the clock monitor circuit 1
can be used to shut off the DAC outputs. The corresponding alarms,
alarm_dataclk_gone and alarm_output_gone, must not be masked
(i.e.Config7, bit <9> and bit <8> must set to "0").
12 collisiongone_ena When set, the FIFO collision alarms can be used to shut off the DAC 1
outputs. The corresponding alarms, alarm_fifo_collision and
alarm_output_gone, must not be masked (i.e.Config7, bit <13> and
bit <8> must set to "0").
11 Reserved Reserved for factory use. 0
10 Reserved Reserved for factory use. 0
9 Reserved Reserved for factory use. 0
8 Reserved Reserved for factory use. 0
7 sif4_ena When set, the serial interface (SIF) is a 4 bit interface, otherwise it is 0
a 3 bit interface.
6 mixer_ena When set, the mixer block is enabled. 0
5 mixer_gain When set, a 6dB gain is added to the mixer output. 0
4 nco_ena When set, the NCO is enabled. This is not required for coarse mixing. 0
3 revbus When set, the input bits for the data bus are reversed. MSB becomes 0
LSB.
2 Reserved Reserved for factory use. 0
1 twos When set, the input data format is expected to be 2’s complement. 0
When cleared, the input is expected to be offset-binary.
0 Reserved Reserved for factory use. 0
Register name: config3 – Address: 0x03, Default: 0xF000
Register Default
Address Bit Name Function
Name Value
config3 0x03 15:12 coarse_dac(3:0) Scales the output current in 16 equal steps. 1111
11:8 Reserved Reserved for factory use. 0000
7:1 Reserved Reserved for factory use. 0000000
0 sif_txenable When set, the internal value of TXENABLE is set to “1”. 0
To enable analog output data transmission, set sif_txenable to “1” or
pull CMOS TXENABLE pin (A32) to high. To disable analog output,
set sif_txenable to “0” and pull CMOS TXENABLE pin (A32) to low.
Register name: config4 – Address: 0x04, Default: No RESET Value (WRITE TO CLEAR)
Register Default
Address Bit Name Function
Name Value
config4 0x04 15:0 iotest_results(15:0) This register is used with pattern checker test enabled (iotest_ena in config1, No RESET
bit<15> set to “1”). It does not have a default RESET value. Value
The values of these bits tell which bit in the word failed during the pattern
checker test. iotest_results(15:8) correspond to the data bits on D[15:8] and
iotest_results(7:0) correspond to the data bits on D[7:0].
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