Datasheet

DAC3484
SLAS749C –MARCH 2011–REVISED AUGUST 2012 www.ti.com
REGISTER DESCRIPTIONS
Register name: config0 – Address: 0x00, Default: 0x049C
Register Default
Address Bit Name Function
Name Value
config0 0x00 15 qmc_offsetAB_ena When set, the digital Quadrature Modulator Correction (QMC) offset 0
correction for the AB data path is enabled.
14 qmc_offsetCD_ena When set, the digital Quadrature Modulator Correction (QMC) offset 0
correction for the CD data path is enabled.
13 qmc_corrAB_ena When set, the QMC phase and gain correction circuitry for the AB 0
data path is enabled.
12 qmc_corrCD_ena When set, the QMC phase and gain correction circuitry for the CD 0
data path is enabled.
11:8 interp(3:0) These bits define the interpolation factor 0100
interp Interpolation Factor
0000 1x
0001 2x
0010 4x
0100 8x
1000 16x
7 fifo_ena When set, the FIFO is enabled. When the FIFO is disabled, 1
DACCCLKP/N and DATACLKP/N must be aligned (not
recommended).
6 Reserved Reserved for factory use. 0
5 Reserved Reserved for factory use. 0
4 alarm_out_ena When set, the ALARM pin becomes an output. When cleared, the 1
ALARM pin is 3-stated.
3 alarm_out_pol This bit changes the polarity of the ALARM signal. 1
MM 0: Negative logic
MM 1: Positive logic
2 clkdiv_sync_ena When set, enables the syncing of the clock divider using the sync 1
source selected by register config32. The internal divided-down
clocks will be phase aligned after syncing. Refer to the Power-Up
Sequence section for more detail.
1 invsincAB_ena When set, the inverse sinc filter for the AB data is enabled. 0
0 invsincCD_ena When set, the inverse sinc filter for the CD data is enabled. 0
32 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links: DAC3484