Datasheet

rwb
A6
A5
A4
A3
A2 A1
A0
D15
D14
D13
D12 D11
D10 D9 D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12 D11
D10 D9 D8
D7
D6
D5
D4
D3
D2
D1
D0
t
d(Data)
SDENB
SCLK
SDIO
SDO
SDENB
SCLK
Instruction Cycle Data Transfer Cycle
T0522-01
SDIO
SDO
Data n – 1
Data n
DAC3484
www.ti.com SLAS749C –MARCH 2011–REVISED AUGUST 2012
Figure 51 shows the serial interface timing diagram for a DAC3484 read operation. SCLK is the serial interface clock input to DAC3484. Serial data
enable SDENB is an active low input to DAC3484. SDIO is serial data in during the instruction cycle. In 3 pin configuration, SDIO is data out from the
DAC3484 during the data transfer cycle, while SDO is in a high-impedance state. In 4 pin configuration, SDO is data out from the DAC3484 during the
data transfer cycle. At the end of the data transfer, SDIO and SDO will output low on the final falling edge of SCLK until the rising edge of SDENB when
they will 3-state.
Figure 51. Serial Interface Read Timing Diagram
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