Datasheet

100100
Pattern Test
100
Frame Strobe and
Optional Parity
D15P
D15N
•
•
•
•
•
•
D0P
D0N
FRAMEP
FRAMEN
TXENABLE
LVDS
LVDS
LVDS
100
SYNCP
SYNCN
LVDS
100
PARITYP
PARITYN
LVDS
AVDD
De-interleave
16
16
16
Control Interface
Temp
Sensor
B0464-01
•
•
•
OSTRP
OSTRN
SDO
SDIO
SDENB
SCLK
RESETB
AVDD
GND
LVPECL
8 Sample FIFO
16
ALARM
SLEEP
Programmable Delay
TESTMODE
IOVDD
Complex Mixer
(FMIX or CMIX)
AB-QMC
Gain and Phase
16-b
DACB
16-b
DACA
IOUTAP
IOUTAN
IOUTBP
IOUTBN
QMC
B-offset
QMC
A-offset
x2 x2 x2 x2
x2 x2 x2 x2
FIR1FIR0
x
sin(x)
x
sin(x)
DAC
Gain
FIR3FIR2
AB-Channel
FIR4
2x–16x Interpolation
AB
32-Bit NCO
cos sin
CMIX Control
(±n*Fs/8)
59 taps 23 taps 11 taps 11 taps 9 taps
A-Group
Delay
B-Group
Delay
Clock Distribution
EXTIO
BIASJ
DACCLKP
DACCLKN
DATACLKP
DATACLKN
CLKVDD DIGVDD VFUSE DACVDD
LVPECL
100
LVDS
Programmable
Delay
Low Jitter
PLL
LPF PLLAVDD
1.2-V
Reference
CD
32-Bit NCO
cos sin
Complex Mixer
(FMIX or CMIX)
CD-QMC
Gain and Phase
16-b
DACD
16-b
DACC
IOUTCP
IOUTCN
IOUTDP
IOUTDN
QMC
D-offset
QMC
C-offset
x2 x2 x2 x2
x2 x2 x2 x2
FIR1FIR0
x
sin(x)
x
sin(x)
FIR3FIR2
CD-Channel
FIR4
59 taps 23 taps 11 taps 11 taps 9 taps
C-Group
Delay
D-Group
Delay
DAC3484
SLAS749C –MARCH 2011–REVISED AUGUST 2012 www.ti.com
FUNCTIONAL BLOCK DIAGRAM
2 Copyright © 2011–2012, Texas Instruments Incorporated