Datasheet

DAC3484
www.ti.com SLAS749C –MARCH 2011–REVISED AUGUST 2012
ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TIMING SYNC INPUT: DACCLKP/N rising edge LATCHING
(4)
Setup time, SYNCP/N valid
t
s(SYNC_PLL)
to rising edge of 200 ps
DACCLKP/N
Hold time, SYNCP/N valid
t
h(SYNC_PLL)
after rising edge of 300 ps
DACCLKP/N
TIMING SERIAL PORT
Setup time, SDENB to rising
t
s(SDENB)
20 ns
edge of SCLK
Setup time, SDIO valid to
t
s(SDIO)
10 ns
rising edge of SCLK
Hold time, SDIO valid to
t
h(SDIO)
5 ns
rising edge of SCLK
Register config6 read (temperature sensor read) 1 µs
t
(SCLK)
Period of SCLK
All other registers 100 ns
Data output delay after
t
d(Data)
10 ns
falling edge of SCLK
Minimum RESETB
t
RESET
25 ns
pulsewidth
(4) SYNC is required to synchronize the PLL circuit in mulitple devices. The SYNC signal must meet the timing relationship with respect to
the reference clock (DACCLKP/N) of the on-chip PLL circuit.
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