Datasheet

DAC3484
SLAS749C –MARCH 2011–REVISED AUGUST 2012 www.ti.com
ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUT TIMING SPECIFICATIONS
Timing LVDS inputs: D[15:0]P/N, FRAMEP/N, SYNCP/N, PARITYP/N, double edge latching
Config36 Setting
0 0 150
0 1 100
0 2 50
0 3 0
0 4 –50
0 5 –100
FRAMEP/N reset and frame indicator latched on
Setup time, D[15:0]P/N,
0 6 –150
rising edge of DATACLKP/N.
FRAMEP/N, SYNCP/N and
t
s(DATA)
ps
PARITYP/N, valid to either
FRAMEP/N parity bit latched on falling edge of
0 7 –200
edge of DATACLKP/N
DATACLKP/N.
1 0 200
2 0 250
3 0 300
4 0 350
5 0 400
6 0 450
7 0 500
Config36 Setting
0 0 350
0 1 400
0 2 450
0 3 500
0 4 550
0 5 600
FRAMEP/N reset and frame indicator latched on
Hold time, D[15:0]P/N,
0 6 650
rising edge of DATACLKP/N.
FRAMEP/N, SYNCP/N and
t
h(DATA)
ps
PARITYP/N, valid after
FRAMEP/N parity bit latched on falling edge of
0 7 700
either edge of DATACLKP/N
DATACLKP/N.
1 0 300
2 0 250
3 0 200
4 0 150
5 0 100
6 0 50
7 0 0
FRAMEP/N and SYNCP/N
t
(FRAME_SYNC)
f
DATACLK
is DATACLK frequency in MHz 1/2f
DATACLK
ns
pulse width
TIMING OUTPUT STROBE INPUT: DACCLKP/N rising edge LATCHING
(3)
Setup time, OSTRP/N valid
t
s(OSTR)
to rising edge of 0 ps
DACCLKP/N
Hold time, OSTRP/N valid
t
h(OSTR)
after rising edge of 300 ps
DACCLKP/N
(3) OSTR is required in Dual Sync Sources mode. In order to minimize the skew it is recommended to use the same clock distribution
device such as Texas Instruments CDCE62005 to provide the DACCLK and OSTR signals to all the DAC3484 devices in the system.
Swap the polarity of the DACCLK outputs with respect to the OSTR ones to establish proper phase relationship.
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