Datasheet

DAC3484
www.ti.com SLAS749C –MARCH 2011–REVISED AUGUST 2012
ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LVDS INPUTS: D[15:0]P/N, DATACLKP/N, FRAMEP/N, SYNCP/N, PARITYP/N
(1)
Logic high differential input
V
A,B+
200 mV
voltage threshold
Logic low differential input
V
A,B–
–200 mV
voltage threshold
V
COM
Input Common Mode 1.0 1.2 1.6 V
Z
T
Internal termination 85 110 135 Ω
C
L
LVDS Input capacitance 2 pF
Interleaved LVDS data
f
INTERL
1250 MSPS
transfer rate
f
DATA
Input data rate 312.5 MSPS
CLOCK INPUT (DACCLKP/N)
Duty cycle 40% 60%
Differential voltage
(2)
|DACCLKP - DACCLKN| 0.4 1.0 V
Internally biased common-
0.2 V
mode voltage
Single-ended swing level –0.4 V
DACCLKP/N Input
1250 MHz
Frequency
OUTPUT STROBE (OSTRP/N)
f
DACCLK
f
OSTR
= f
DACCLK
/ (n x 8 x Interp) where n is any positive integer, /
f
OSTR
Frequency MHz
f
DACCLK
is DACCLK frequency in MHz (8 x
interp)
Duty cycle 50%
Differential voltage |OSTRP – OSTRN| 0.4 1.0 V
Internally biased common-
0.2 V
mode voltage
Single-ended swing level –0.4 V
CMOS INTERFACE: ALARM, SDO, SDIO, SCLK, SDENB, SLEEP, RESETB, TXENABLE
V
IH
High-level input voltage 2 V
V
IL
Low-level input voltage 0.8 V
I
IH
High-level input current -40 40 µA
I
IL
Low-level input current -40 40 µA
C
I
CMOS Input capacitance 2 pF
IOVDD –
I
load
= –100 μA V
0.2
V
OH
ALARM, SDO, SDIO
I
load
= –2 mA 0.8 x IOVDD V
I
load
= 100 μA 0.2 V
V
OL
ALARM, SDO, SDIO
I
load
= 2 mA 0.5 V
(1) See LVDS INPUTS section for terminology.
(2) Driving the clock input with a differential voltage lower than 1 V may result in degraded performance.
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