Datasheet

DAC3484
SLAS749C MARCH 2011REVISED AUGUST 2012
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ELECTRICAL CHARACTERISTICS – DC SPECIFICATIONS
(1)
(continued)
over recommended operating free-air temperature range, nominal supplies, IOUT
FS
= 20mA (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
(3)
AVDD, IOVDD, PLLAVDD All Conditions 3.14 3.3 3.46 V
DIGVDD All Conditions 1.14 1.2 1.32 V
F
DAC
Sampling Rate 1.25GSPS, PLL OFF
1.14 1.2 1.32
F
DAC
Sampling Rate 1GSPS, PLL ON
CLKVDD, DACVDD V
F
DAC
Sampling Rate > 1GSPS, PLL ON 1.25 1.29 1.32
PSRR Power Supply Rejection Ratio DC tested ±0.2 %FSR/V
POWER CONSUMPTION
I
(AVDD)
Analog supply current
(4)
123 135 mA
MODE 1
I
(DIGVDD)
Digital supply current 595 650 mA
f
DAC
= 1.25GSPS, 4x interpolation, Mixer on,
I
(DACVDD)
DAC supply current 35 50 mA
QMC on, invsinc on, PLL enabled, 20mA FS
I
(CLKVDD)
Clock supply current 90 95 mA
output, IF = 200MHz
P Power dissipation 1270 1320 mW
I
(AVDD)
Analog supply current
(4)
107 mA
MODE 2
I
(DIGVDD)
Digital supply current 595 mA
f
DAC
= 1.25GSPS, 4x interpolation, Mixer on,
I
(DACVDD)
DAC supply current 38 mA
QMC on, invsinc on, PLL disabled, 20mA FS
I
(CLKVDD)
Clock supply current 71 mA
output, IF = 200MHz
P Power dissipation 1198 mW
I
(AVDD)
Analog supply current
(4)
107 mA
MODE 3
I
(DIGVDD)
Digital supply current 282 mA
f
DAC
= 625MSPS, 2x interpolation, Mixer on,
I
(DACVDD)
DAC supply current 20 mA
QMC on, invsinc off, PLL disabled, 20mA FS
I
(CLKVDD)
Clock supply current 41 mA
output, IF = 200MHz
P Power dissipation 765 mW
I
(AVDD)
Analog supply current
(4)
35 mA
MODE 4
I
(DIGVDD)
Digital supply current 595 mA
f
DAC
= 1.25GSPS, 4x interpolation, Mixer on,
I
(DACVDD)
DAC supply current 38 mA
QMC on, invsinc on, PLL enabled, Channels
I
(CLKVDD)
Clock supply current 90 mA
A/B/C/D output sleep, IF = 200MHz,
P Power dissipation 984 mW
I
(AVDD)
Analog supply current
(4)
20 mA
Mode 5
I
(DIGVDD)
Digital supply current 10 mA
Power-Down mode: No clock,
I
(DACVDD)
DAC supply current 4 mA
DAC on sleep mode (clock receiver sleep),
Channels A/B/C/D output sleep, static data
I
(CLKVDD)
Clock supply current 10 mA
pattern
P Power Dissipation 95 mW
I
(AVDD)
Analog supply current
(4)
107 mA
Mode 6
I
(DIGVDD)
Digital supply current 333 mA
f
DAC
= 1GSPS, 8x interpolation, Mixer off,
I
(DACVDD)
DAC supply current 35 mA
QMC on, invsinc off, PLL enabled, 20mA FS
I
(CLKVDD)
Clock supply current 60 mA
output, IF = 200MHz
P Power dissipation 867 mW
I
(AVDD)
Analog supply current
(4)
123 mA
Mode 7
I
(DIGVDD)
Digital supply current 323 mA
f
DAC
= 737.28MSPS, 4x interpolation, Mixer on,
I
(DACVDD)
DAC supply current 23 mA
QMC on, invsinc off, PLL enabled, 20mA FS
I
(CLKVDD)
Clock supply current 69 mA
output, IF = 150MHz
P Power dissipation 904 mW
(3) To ensure power supply accuracy and to account for power supply filter network loss at operating conditions, the use of the ATEST
function in register config27 to check the internal power supply nodes is recommended.
(4) Includes AVDD, PLLAVDD, and IOVDD
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