Datasheet

19.2MHz
TCXO
CDCE62005
DAC348X
DATA
DATA _CLK
FRAME
SYNC
PARITY
(LVDS DC Coupled)
DAC_CLK
(LVPECL AC
Coupled)
OSTR_CLK
(LVPECL AC
Coupled)
FPGA CLK
· TSW3100 or TSW1400
· LVDS AC coupled
J10
Ext. CLK Output
6V Only
J18
Power
Supply
Circuits
J11
A
B
C
D
J9
Ext. CLK Input
· 1.3Vp Single Ended Max
· 1.5GHz Max
· Primary Reference
· (LVPECL AC coupled )
19.2MHz Reference
· LVCMOS Level
· Secondary Reference for
CDCE62005 PLL Mode
Y4
Y3
Y
B
* Y
A
*
PRI
SEC
J6
+
J2
+
J7
+
_
J3
+
_
_
_
FPGA CLK 2
· Required for TSW1400 interface with DAC34H84 and DAC34SH84
· LVDS AC coupled
Clock routing is optimized for layout depending
on the clock input pin out location.
Y
A
* =
· Y1 for DAC3484 and DAC3482 EVMs
· Y2 for DAC34H84 and DAC34SH84 EVMs
Y
B
* =
· Y2 for DAC3484 and DAC3482 EVMs
· Y1 for DAC34H84 and DAC34SH84 EVMs
5
th
Order LPF
5
th
Order LPF
5
th
Order LPF
5
th
Order LPF
Note: 5
th
Order LPF is bypassed by default
DAC3482 Outputs
www.ti.com Software Control
Figure 1. DAC348x EVM Block Diagram
2 Software Control
2.1 Installation Instructions
• Open folder named DAC348x_Installer_vxpx (xpx represents the latest version)
• Run Setup.exe
• Follow the on-screen instructions
• Once installed, launch the program by clicking on the DAC348x_GUI_vxpx program in Start>Texas
Instruments DACs. The installation directory is located at C:\Program Files\Texas
3
SLAU432–February 2012 DAC348x EVM
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