Datasheet

DAC3152
DAC3162
SLAS736D –NOVEMBER 2010–REVISED AUGUST 2012 www.ti.com
ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS
DVDD18 = CLKVDD18 = 1.8 V, AVDD33 = 3.3 V, f
DAC
= 500 MSPS, f
OUT
= 1 MHz over recommended operating free-air
temperature range, IOUT
FS
= 20 mA (unless otherwise noted)
DAC3152 DAC3162
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX
LVDS INPUTS: DIGITAL INPUT DATA
(1)
Logic-high differential input voltage
V
A,B+
150 400 150 400 mV
threshold
Logic-low differential input voltage
V
A,B–
–400 –150 –400 –150 mV
threshold
V
COM
Input common mode 0.9 1.2 1.5 0.9 1.2 1.5 V
Z
T
Internal termination 85 110 135 85 110 135 Ω
C
L
LVDS input capacitance 2 2 pF
f
INTERL
Interleaved LVDS data rate 1000 1000 MSPS
f
DATA
Input data rate (per DAC) 500 500 MSPS
CLOCK INPUT: DACCLKP/N
Duty cycle 40% 60% 40% 60%
Differential voltage 0.2 1 0.2 1 V
Clock frequency 500 500 MHz
CMOS INTERFACE: SLEEPB
V
IH
High-level input voltage 2 2 V
V
IL
Low-level input voltage 0.8 0.8 V
I
IH
High-level input current -40 40 -40 40 µA
I
IL
Low-level input current -40 40 -40 40 µA
C
I
CMOS Input capacitance 2 2 pF
DIGITAL INPUT DATA TIMING SPECIFICATIONS: DOUBLE EDGE LATCHING
Setup time, valid to either edge of
t
s(DATA)
200 200 ps
DACCLKP/N
Hold time, valid after either edge of
t
h(DATA)
200 200 ps
DACCLKP/N
(1) See LVDS INPUTS section for terminology.
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