Datasheet
DAC3152
DAC3162
SLAS736D –NOVEMBER 2010–REVISED AUGUST 2012
www.ti.com
REFERENCE OPERATION
The DAC3152/DAC3162 uses a band-gap reference and control amplifier for biasing the full-scale output current.
The full-scale output current is set by applying an external resistor R
BIAS
to pin BIASJ. The bias current I
BIAS
through resistor R
BIAS
is defined by the on-chip band-gap reference voltage and control amplifier. The default full-
scale output current equals 16 times this bias current and can thus be expressed as:
IOUT
FS
= 16 × I
BIAS
= 16 × V
BG
/ R
BIAS
The band-gap reference voltage delivers an accurate voltage of 1.2 V. The full-scale output current can be
adjusted from 20 mA down to 2 mA by varying resistor RBIAS. The internal control amplifier has a wide input
range, supporting the full-scale output current range of 20 dB. The recommended value for R
BIAS
is 960 Ω, which
results in a full-scale output current of 20 mA.
DAC TRANSFER FUNCTION
The DAC outputs of the DAC3152/DAC3162 consist of a segmented array of NMOS current sinks, capable of
sinking a full-scale output current up to 20 mA. Differential current switches direct the current to either one of the
complementary output nodes IOUTP or IOUTN. Complementary output currents enable differential operation,
thus canceling out common-mode noise sources (digital feed-through, on-chip and PCB noise), dc offsets, and
even-order distortion components, and increasing signal output power by a factor of four.
The full-scale output current is set using external resistor R
BIAS
in combination with an on-chip band-gap voltage
reference source (1.2 V) and control amplifier. Current I
BIAS
through resistor R
BIAS
is mirrored internally to provide
a maximum full-scale output current equal to 16 times I
BIAS
.
The relation between IOUTP and IOUTN can be expressed as:
IOUT
FS
= IOUTP + IOUTN
Current flowing into a node is denoted as – current, and current flowing out of a node as + current. Because the
output stage is a current sink, the current flows from AVDD33 into the IOUTP and IOUTN pins. The output
current flow in each pin driving a resistive load can be expressed as:
IOUTP = IOUT
FS
× ((2
N
– 1) – CODE) / 2
N
IOUTN = IOUT
FS
× CODE / 2
N
where CODE is the decimal representation of the DAC data input word and N is the DAC bit resolution.
For the case where IOUTP and IOUTN drive resistor loads R
L
directly, this translates into single-ended voltages
at IOUTP and IOUTN:
VOUTP = AVDD – | IOUTP | × R
L
VOUTN = AVDD – | IOUTN | × R
L
Assuming that the data is full scale (2
N
– 1 in offset binary notation) and the R
L
is 25 Ω, the differential voltage
between pins IOUTP and IOUTN can be expressed as:
VOUTP = AVDD – | – 0 mA | × 25 Ω = 3.3 V
VOUTN = AVDD – | –20 mA | × 25 Ω = 2.8 V
VDIFF = VOUTP – VOUTN = 0.5 V
Note that care should be taken not to exceed the compliance voltages at nodes IOUTP and IOUTN, which would
lead to increased signal distortion.
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