Datasheet

SLEEPB
internal
digital in
AVDD33
GND
400 Ω
100 kΩ
100
LVDS
Receiver
DAC
GND
V
COM
=
(V
A
+V
B
)/2
V
B
V
A,B
V
A
V
A
V
B
V
A,B
Logical Bit
Equivalent
1.4 V
1 V
400 mV
0 V
–400 mV
1
0
Example
LVDS
Receiver
GND
DVDD18
100 Ω
internal
digital in
DAC3152
DAC3162
www.ti.com SLAS736D –NOVEMBER 2010–REVISED AUGUST 2012
DATA INPUTS
The input data LVDS pairs (D[11:0]P/N) have the input configuration shown in Figure 38. Figure 39 shows the
typical input levels and common-mode voltage used to drive these inputs.
Figure 38. D[13:0]P/N LVDS Input Configuration
Figure 39. LVDS Data Input Levels
Table 1.
Resulting Differential Resulting
Applied Voltages
Logical Bit
Voltage Common-Mode Voltage
Binary Equivalent
V
A
V
B
V
A,B
V
COM
1.4 V 1 V 400 mV 1
1.2 V
1 V 1.4 V –400 mV 0
1.2 V 0.8 V 400 mV 1
1 V
0.8 V 1.2 V –400 mV 0
CMOS INPUT
Figure 40 shows a schematic of the SLEEPB equivalent CMOS digital inputs. See the specification table for logic
thresholds. The pullup circuitry is approximately equivalent to 100 kΩ.
Figure 40. SLEEPB Digital Equivalent Input
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