Datasheet

DACCLKP
1 : 1
DACLCKN
C
AC
0.01 µF
Optional, reduces
clock feedthrough
R
opt
22 Ω
TTL/CMOS
source
DACCLKP
DACLCKN
0.01 µF
R
opt
22 Ω
TTL/CMOS
source
DACCLKP
1 : 4
DACLCKN
Optional, may be bypassed
for sine-wave input
R
T
200 Ω
C
0.1 µF
AC
DAC3152
DAC3162
SLAS736D –NOVEMBER 2010–REVISED AUGUST 2012 www.ti.com
A single-ended clock, such as a clean sinusoid or a 1.8 V LVCMOS signal (for low-rate operation), can also be
used to drive the clock if configured as in the input circuits of Figure 36 and Figure 37.
Figure 36. Clock Input Configuration Using 50-Ω Cable Input
Figure 37. Clock Input Configuration With a Single-Ended TTL/CMOS Clock
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Product Folder Links: DAC3152 DAC3162