Datasheet

C
AC
DACCLKP
DACCLKN
0.1 Fm
0.1 Fm
100 W
Differential LVDS
Source
V
TT
R
PU
R
PD
C
AC
DACCLKP
DACCLKN
0.1 Fm
0.1 Fm
100 W
Differential ECL or
(LV)PECL Source
R and R are chosen
based on the clock driver
PU PD
DACCLKP
DACCLKN
GND
500 Ω
2 kΩ
CLKVDD
Note: Input common mode level is
approximately 1/2 CLKVDD18,
or 0.9 V nominal.
´
2 kΩ
500 Ω
DAC3152
DAC3162
www.ti.com SLAS736D –NOVEMBER 2010–REVISED AUGUST 2012
CLOCK INPUT
The DAC clock (DACCLKP/N) is an internally biased differential input that for optimal performance should be
driven by a low-jitter clock source. The DACCLK signal is used for both data latching (in DDR format) and as the
data conversion clock. Figure 33 shows an equivalent circuit for the DAC input clock.
Figure 33. DACCLKP/N Equivalent Input Circuit
The preferred configuration for driving the DACCLK input consists of a differential ECL/PECL source as shown in
Figure 34. Although not optimal due to the limited signal swing, an LVDS source can also be used to drive the
clock input with the preferred configuration shown in Figure 35.
Figure 34. Clock Input Configuration LVPECL
Figure 35. Clock Input Configuration LVDS
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