Datasheet

A
1
B
1
A
2
B
2
B
0
B
3
A
4
B
4
A
3
B
5
A
6
A
5
B
6
A
7
B
7
A
8
A
0
DATA
DACCLKP/N
(DDR)
Write A
1
to DACA on rising
edge
Write B
1
to DACB on
falling edge
Sample 0
t
s(DATA)
t
h(DATA)
t
s(DATA )
t
h(DATA)
Sample 1
DAC3152
DAC3162
SLAS736D –NOVEMBER 2010–REVISED AUGUST 2012 www.ti.com
APPLICATION INFORMATION
DATA INTERFACE
The parallel-port data interface to the device consists of a single LVDS bus that accepts interleaved A and B data
with up to 12-bit resolution. Data is sampled by the LVPECL double-data-rate (DDR) clock DACCLK. DACCLK is
additionally used for the data conversion process, and hence a low-jitter source is recommended. Setup and hold
requirements must be met for proper sampling.
The interleaved data for channels A and B is interleaved in the form A0, B0, A1, B1… into the data bus. Data into
the device is formatted according to the diagram shown in Figure 32.
Figure 32. Data Transmission Format
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