Datasheet

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SBAS279D − AUGUST 2003 − REVISED JULY 2005
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7
SCLK
DB15 DB0
SYNC
DIN
t
1
t
2
t
7
t
3
t
4
t
8
t
5
t
6
Figure 2. Serial Write Operation of V-DAC
TIMING REQUIREMENTS
(1,2)
: V-DAC
PARAMETER DESCRIPTION MIN TYP MAX UNIT
t
1
(3)
SCLK cycle time 50 ns
t
2
SCLK high time 13 ns
t
3
SCLK low time 22.5 ns
t
4
SYNC to SCLK rising edge setup time 0 ns
t
5
Data setup time 5 7.5 ns
t
6
Data hold time 1.5 2.5 ns
t
7
SCLK falling edge to SYNC rising edge 0 −6.0 ns
t
8
Minimum SYNC high time 50 ns
PDV fall time to V
OUT
(V-DAC coming out of power-down mode) 8 μs
(1)
All input signals are specified with t
r
= t
f
≤ 2ns (10% to 90% of +V
DV
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2)
Based on design simulation and characterization; not production tested.
(3)
Maximum SCLK frequency is 20MHz at +V
AV
= +V
DV
= +2.7V to 3.3V.
V−DAC: SERIAL DATA INPUT FORMAT
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
A0
DAC1
A1
DAC2
A2
DAC3
A3
DAC4
D11
(MSB)
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(LSB)
Address Bits 12-Bit Data Word
NOTE: A logic high in the address bit will select the corresponding V-DAC and write the data word into its register. If more than one address bit
is set high, the selected V-DACs are updated with the same data word simultaneously.