Datasheet


SBAS279D − AUGUST 2003 − REVISED JULY 2005
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6
TIMING INFORMATION
t
CP
t
CL
t
DO2
t
DO1
t
S1
t
S2
t
H1
t
H2
t
CH
DAC1 (n
−
1)
CLK
I−DAC OUT1
I−DAC OUT2
DAC2 (n
−
1) DAC2 (n) DAC2 (n + 1)DAC1 (n) DAC1 (n +1)
(n
−
2)
(n
−
2)
(n
−
1)
(n
−
1)
(n)
(n)
Data In
[D11:D0]
Figure 1. Timing Diagram of I-DAC
TIMING REQUIREMENTS
(1,2)
: I-DAC
PARAMETER DESCRIPTION MIN TYP MAX UNIT
t
CP
Clock cycle time (period) 25 ns
t
CL
Clock low time 10 ns
t
CH
Clock high time 10 ns
t
S1
Data setup time, I-DAC1 1 5 ns
t
S2
Data setup time, I-DAC2 1 5 ns
t
H1
Data hold time, I-DAC1 3.35 5 ns
t
H2
Data hold time, I-DAC2 3.35 5 ns
t
DO1
(3)
Output delay time, I-DAC1 t
S1
+ t
CP
ns
t
DO2
(3)
Output delay time, I-DAC2 t
S2
+(t
CP/2
) ns
CS hold time (pulse width) 2.49 ns
CS to clock rising or falling edge setup time 0.52 ns
STBY rise time to I
OUT
17 μs
PD fall time to I
OUT
(I-DAC coming out of power-down mode) 22 μs
(1)
Based on design simulation and characterization; not production tested.
(2)
All input signals are specified with t
r
= t
f
≤ 2ns (10% to 90% of +V
DV
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(3)
Output delay time measured from 50% of rising clock edge to 50% point of full-scale transition.