Datasheet
SBAS279D − AUGUST 2003 − REVISED JULY 2005
www.ti.com
2
ORDERING INFORMATION
PRODUCT PACKAGE-LEAD
PACKAGE
DESIGNATOR
(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
DAC2932
TQFP 48
PFB
40°C to 85°C
DAC2932
DAC2932PFBT Tape and Reel, 250
DAC2932 TQFP-48 PFB −40°C to +85°C
DAC2932
DAC2932PFBR Tape and Reel, 2000
(1)
For the most current specification and package information, refer to our web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
DAC2932 UNIT
+V
A
to AGND −0.3 to +4 V
+V
D
to DGND −0.3 to +4 V
AGND to DGND −0.2 to +0.2 V
+V
A
to +V
D
−0.7 to +0.7 V
CLK, PD, STBY, CS to DGND −0.3 to V
D
+ 0.3 V
D0−D11 to DGND −0.3 to V
D
+ 0.3 V
I
OUT
, I
OUT
to AGND −0.5 to V
A
+ 0.3 V
REFV to AGNDV −0.3 to V
AV
+ 0.3 V
GSET, REF
IN
, FSA to AGND −0.3 to V
A
+ 0.3 V
V
OUT
x to AGNDV −0.3 to V
AV
+ 0.3 V
DIN to DGNDV −0.3 to V
DV
+ 0.3 V
Junction temperature +150 °C
Case temperature +100 °C
Storage temperature range −40 to +150 °C
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
FUNCTIONAL BLOCK DIAGRAM
STBY
CS
DIN
SCLK
SYNC
PD
CLK
Parallel Data Input, 12−Bit Data,
Interleaved
DAC2932
REF
IN
+V
D
+V
A
GSET FSA1 FSA2 AGND DGND
I
OUT1
I
OUT1
I
OUT2
I
OUT2
V
OUT1
V
OUT2
V
OUT3
V
OUT4
+1.22V Reference
Latch
Serial−to−Parallel
Shift Register
Input Latch
and
De−Multiplexer
Reference Control Amp
12−Bit
40MSPS
I−DAC1
DAC
Latch 1
12−Bit
40MSPS
I−DAC2
12−Bit
String−DAC1
Latch
12−Bit
String−DAC2
Latch
12−Bit
String−DAC3
Latch
12−Bit
String−DAC4
DAC
Latch 2
Data2
CLK2
Clock
I−DAC Section
A0
A
A
A
A
Dx12
A1
A2
A3
REFV
+V
DV
+V
AV
AGNDVDGNDVPDV
V−DAC Section
Data1
CLK1
[D11:D0]