Datasheet

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SBAS279D − AUGUST 2003 − REVISED JULY 2005
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19
The DC gain for this circuit is equal to feedback resistor R
F
.
At high frequencies, the DAC output impedance (C
D1
, C
D2
)
produces a zero in the noise gain for the OPA2690 that can
cause peaking in the closed-loop frequency response. C
F
is
added across R
F
to compensate for this noise gain peaking.
To achieve a flat transimpedance frequency response, the
pole in each feedback network should be set to:
1
2pR
F
C
F
+
GBP
Ǹ
4pR
F
C
F
where GBP = gain bandwidth product of the op amp, which
gives a corner frequency f
−3dB
of approximately:
f
*3dB
+
GBP
Ǹ
2pR
F
C
D
The full-scale output voltage is simply defined by the
product of I
OUTFS
• R
F
, and has a negative unipolar
excursion. To improve on the ac performance of this circuit,
adjustment of R
F
and/or I
OUTFS
should be considered.
Further extensions of this application example may
include adding a differential filter at the OPA2690 output
followed by a transformer, in order to convert to a
single-ended signal.
SINGLE-ENDED CONFIGURATION
Using a single load resistor connected to one of the DAC
outputs, a simple current-to-voltage conversion can be
accomplished. The circuit in Figure 33 shows a 250Ω
resistor connected to I
OUT
. Therefore, with a nominal
output current of 2mA, the DAC produces a total signal
swing of 0V to 0.5V.
I
OUT
I
OUT
DAC2932
250
Ω
250
Ω
I
OUTFS
=2mA
V
OUT
=0Vto+0.5V
Figure 33. Differential Output Configuration
Using an RF Transformer
Different load resistor values may be selected, as long as
the output compliance range is not exceeded. Additionally,
the output current (I
OUTFS
) and the load resistor can be
mutually adjusted to provide the desired output signal
swing and performance.
INTERFACING ANALOG QUADRATURE
MODULATORS
One of the main applications for the dual-channel DAC is
baseband I- and Q-channel transmission for digital
communications. In this application, the DAC is followed
by an analog quadrature modulator, modulating an IF
carrier with the baseband data, as shown in Figure 34.
Often, the input stages of these quadrate modulators
consist of npn-type transistors that require a dc bias (base)
voltage of > 0.8V.
I
OUT
1
I
OUT
1
I
OUT
2
I
OUT
2
DAC2932
Signal
Conditioning
I
IN
I
REF
Q
IN
Q
REF
∑
Quadrature Modulator
V
OUT
~0V
P
to 0.5V
P
V
IN
~0.6V
P
to 1.8V
P
RF
I
IN
I
REF
Figure 34. Generic Interface to a Quadrature Modulator. Signal conditioning (level shifting) may be
required to ensure correct dc common-mode levels at the input of the quadrature modulator.
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