Datasheet

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SBAS279D − AUGUST 2003 − REVISED JULY 2005
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15
DAC TRANSFER FUNCTION
Each of the I-DACs in the DAC2932 has a complementary
current output, I
OUT1
and I
OUT2
. The full-scale output
current, I
OUTFS
, is the summation of the two
complementary output currents:
I
OUTFS
+ I
OUT
) I
OUT
The individual output currents depend on the DAC code
and can be expressed as:
I
OUT
+ I
OUTFS
(Codeń4096)
I
OUT
+ I
OUTFS
(4095 * Code)ń4096
where Code is the decimal representation of the DAC data
input word (0 to 4095).
Additionally, I
OUTFS
is a function of the reference current
I
REF
, which is determined by the reference voltage and the
external setting resistor, R
SET
.
I
OUTFS
+ 32 I
REF
+ 32
V
REF
R
SET
In most cases, the complementary outputs will drive
resistive loads or a terminated transformer. A signal
voltage will develop at each output according to:
V
OUT
+ I
OUT
R
LOAD
V
OUT
+ I
OUT
R
LOAD
The value of the load resistance is limited by the output
compliance specification of the DAC2932. To maintain
optimum linearity performance, the compliance voltage at
I
OUT
and I
OUT
should be limited to +0.5V or less.
The two single-ended output voltages can be combined to
find the total differential output swing:
V
OUTDIFF
+ V
OUT
* V
OUT
+
(2 Code * 4095)
4096
I
OUTFS
R
LOAD
POWER-DOWN MODES
The DAC2932 has several modes of operation. Besides
normal operation, the I-DAC section features a Standby
mode and a full power-down mode, while the V-DAC
section has one power-down mode. All modes are
controlled by appropriate logic levels on the assigned pins
of the DAC2932. Table 1 lists all pins and possible modes.
The pins have internal pull-ups or pull-downs; if left open,
all pins will resume logic levels that place the I-DAC and
V-DAC in a normal operating mode (fully functional).
When in Standby mode the analog functions of the I-DAC
section are powered down. The internal logic is still active
and will consume some power if the clock remains applied.
To further reduce the power in Standby mode the CS
pin
may be pulled high, which disables the internal logic from
being clocked, even with the clock signal applied.
If CS
remains low during the Standby mode and a running
clock remains applied, any new data on the parallel data
port will be latched into the DAC. The analog output,
however, will not be updated as long as the I-DACs remain
in Standby mode.
Table 1. Power-Down Modes
PD (16) STBY(17) CS (18) PDV (44) DAC MODE DAC OUTPUTS
0 0 0 X I-DAC enabled Standby; data can still be written into the DACs
with running clock applied
High-Z
0 0 1 X I-DAC disabled Standby; writing into DAC disabled—clock input
disabled by CS
High-Z
0 1 0 X I-DAC enabled Normal operation (return from Standby) Last state prior to
Standby
0 1 1 X I-DAC disabled Data input and clock input disabled; use when
multiple devices on one bus
Last data held
1 X X X I-DAC disabled Full power-down; STBY and CS have no effect High-Z
0 X X 0 V-DAC enabled V-DAC normal operation
X X X 1 V-DAC disabled V-DAC in power-down mode; independent
operation of any I-DAC power-down
configuration
All outputs; High-Z
NOTE: X = don’t care.
(1)
(2)
(3)
(4)
(5)
(6)
(7)