Datasheet

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SBAS279D − AUGUST 2003 − REVISED JULY 2005
www.ti.com
14
APPLICATION INFORMATION
THEORY OF OPERATION
The architecture of the DAC2932 uses the current steering
technique to enable fast switching and a high update rate.
The core element within the monolithic DAC is an array of
segmented current sources that are designed to deliver a
full-scale output current of up to 2mA, as shown in
Figure 27. An internal decoder addresses the differential
current switches each time the DAC is updated and a
corresponding output current is formed by steering all
currents to either output summing node, I
OUT
or I
OUT
. The
complementary outputs deliver a differential output signal,
which improves the dynamic performance through
reduction of even-order harmonics and common-mode
signals (noise), and doubles the peak-to-peak output
signal swing by a factor of two, compared to single-ended
operation.
The segmented architecture results in a significant
reduction of the glitch energy, and improves the dynamic
performance (SFDR) and DNL. The current outputs
maintain a very high output impedance of greater than
200kΩ.
The full-scale output current is determined by the ratio of
the internal reference voltage (approximately +1.2V) and
an external resistor, R
SET
. The resulting I
REF
is internally
multiplied by a factor of 32 to produce an effective DAC
output current that can range from 0.5mA to 2mA,
depending on the value of R
SET
.
The DAC2932 is split into a digital and an analog portion,
each of which is powered through its own supply pin. The
digital section includes edge-triggered input latches and
the decoder logic, while the analog section comprises the
current source array with its associated switches, and the
reference circuitry.
STBY
CS
DIN
SCLK
SYNC
PD
CLK
12−Bit Data,
Interleaved
DAC2932
REF
IN
+V
D
+V
A
GSET FSA1 FSA2 AGND DGND
I
OUT1
I
OUT1
I
OUT2
I
OUT2
V
OUT1
V
OUT2
V
OUT3
V
OUT4
+1.22V Reference
Latch
Serial−to−Parallel
Shift Register
Input Latch
and
De−Multiplexer
Reference Control Amp
12−Bit
40MSPS
I−DAC1
DAC
Latch 1
12−Bit
40MSPS
I−DAC2
12−Bit
String−DAC1
Latch
12−Bit
String−DAC2
Latch
12−Bit
String−DAC3
Latch
12−Bit
String−DAC4
DAC
Latch 2
Data2
CLK2
Clock
I−DAC Section
A0
A
A
A
A
Dx12
A1
A2
A3
REFV
+V
DV
+V
AV
AGNDVDGNDVPDV
V−DAC Section
Data1
CLK1
Parallel Data Input
[D11:D0]
Figure 27. Block Diagram of the DAC2932