Datasheet

DAC2902
5
SBAS167C
www.ti.com
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
S
Input Setup Time 2 ns
t
H
Input Hold Time 1.5 ns
t
LPW,
t
CPW
Latch/Clock Pulsewidth 3.5 4 ns
t
CW
Delay Rising CLK Edge to 0 t
PW
– 2ns
Rising WRT Edge
t
PD
Propagation Delay 1 ns
t
SET
Settling Time (0.1%) 30 ns
TIMING DIAGRAM
t
PD
t
H
t
LPW
t
CPW
t
CW
t
SET
D[11:0]
(n)
D[11:0]
(n + 1)
t
S
I
OUT(n)
I
OUT(n +1)
50%
DATA IN
WRT1
WRT2
CLK1
CLK2
I
OUT
1
I
OUT
2
DIGITAL INPUTS AND TIMING
The data input ports of the DAC2902 accept a standard
positive coding with data bit D11 being the most significant
bit (MSB). The converter outputs support a clock rate of up
to 125MSPS. The best performance will typically be achieved
with a symmetrical duty cycle for write and clock; however,
the duty cycle may vary as long as the timing specifications
are met. Also, the setup and hold times may be chosen
within their specified limits.
All digital inputs of the DAC2902 are CMOS-compatible.
The logic thresholds depend on the applied digital supply
voltages, such that they are set to approximately half the
supply voltage: V
th
= +V
D
/2 (±20% tolerance). The DAC2902
is designed to operate with a digital supply (+V
D
) of +3.0V
to +5.5V.
The two converter channels within the DAC2902 consist of
two independent, 12-bit, parallel data ports. Each DAC
channel is controlled by its own set of write (WRT1, WRT2)
and clock (CLK1, CLK2) inputs. Here, the WRT lines
control the channel input latches and the CLK lines control
the DAC latches. The data is first loaded into the input latch
by a rising edge of the WRT line. This data is presented to
the DAC latch on the following falling edge of the WRT
signal. On the next rising edge of the CLK line, the DAC is
updated with the new data and the analog output signal will
change accordingly. The double latch architecture of the
DAC2902 results in a defined sequence for the WRT and
CLK signals, expressed by parameter t
CW
. A correct timing
is observed when the rising edge of CLK occurs at the same
time, or before, the rising edge of the WRT signal. This
condition can simply be met by connecting the WRT and
CLK lines together. Note that all specifications were mea-
sured with the WRT and CLK lines connected together.