Datasheet

D23 D0
SCLK
SDI
CS
t
L
t
H
1/f
SCLK
||
|
|
|
||
1 2 21 22 23 24
PD23 PD0
SDO
|
|
|
t
CSB
|
PD0
DAC161S055
www.ti.com SNAS503B –NOVEMBER 2010–REVISED JANUARY 2012
DIGITAL INTERFACE TIMING CHARACTERISTICS
These specifications apply for V
A
= 2.7V to 5.25V, VDDIO = 1.7V to V
A
, C
L
= 200 pF. Boldface limits apply for T
A
= −40°C
to 105°C. All other limits apply to T
A
= 25°C, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
f
SCLK
VDDIO=1.7V to 2.7V 0 10 MHz
SCLK Frequency
VDDIO=2.7V to 5.25V 0 20
t
H
SCLK High Time 15 25
t
L
SCLK Low Time 20 25
t
CSB
VDDIO=1.7V to 2.7V 75
CSB High Pulse width
VDDIO=2.7V to 5.25V 40
t
CSS
CSB Set-up Time Prior to SCLK Rising 10
edge
t
CSH
CSB Hold Time after the 24th Falling 0
Edge of SCLK
t
ZSDO
CSB Falling Edge to SDO Valid VDDIO=1.8V 40
VDDIO=3V 10
VDDIO=5V 6
t
SDOZ
CSB Rising Edge to SDO HiZ VDDIO=1.8V 75
VDDIO=3V 40
ns
VDDIO=5V 27
t
CLRS
CSB Rising Edge to CLRB Falling CLRB must not transition anytime CSB 5
Edge is low.
t
LDACS
CSB Rising Edge to LDACB Falling LDACB must not transition anytime CSB 5
Edge is low.
t
LDAC
LDACB Low Time 10 2.5
t
CLR
CLRB Low Time 10 2.5
t
DS
SDI Data Set-up Time prior to SCLK 10
Rising Edge
t
DH
SDI Data Hold Time after SCLK Rising 0
Edge
t
DO
SDO Output Data Valid VDDIO=1.7 62
VDDIO=3.3 25
VDDIO=5 15
TIMING DIAGRAMS
Figure 1. DAC161S055 Input/Output Waveforms
Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: DAC161S055