Datasheet

TO OUT DRIVE
TO OUT DRIVE
DAC161S055
www.ti.com SNAS503B –NOVEMBER 2010–REVISED JANUARY 2012
PIN DESCRIPTIONS (continued)
Pin #
Pin Name ESD Structure Type Function and Connection
WQFN-16
VOUT 2 Analog Output DAC output.
VREF 6 Analog Input Voltage Reference Input.
GND 7 Ground Ground (Analog and Digital).
SDI 11 Digital Input SPI data input .
Chip select signal for SPI interface. On the falling edge of
CSB 12 Digital Input CSB the chip begins to accept data and output data with
the SCLK signal. This pin is active low.
SCLK 10 Digital Input Serial data clock for SPI Interface.
SDO 9 Digital Output Data Out for daisy chain or data read back verification.
Load DAC signal. This signal transfers DAC data from
LDACB 13 Digital Input the SPI input register to the DAC output register. The
signal is active low.
Asynchronous Reset. If this pin is pulled low, the output
CLRB 14 Digital Input will be updated to its power up condition set by the MZB
pin. This pin is active low.
Power up at Zero/Mid-scale. Tie this pin to GND to power
MZB 15 Digital Input
up to Zero or to VA to power up to mid-scale.
No connect pins. Connect to GND in board layout will
NC 3,4,5,8
result in the lowest amount of coupled noise.
Attach die attach paddle to GND for best noise
DAP DAP
performance.
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