Datasheet

DAC161S055

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SNAS503B –NOVEMBER 2010–REVISED JANUARY 2012

INSTRUCTION SET

The instruction set for the DAC161S055 is common to the family of single and multi channel devices (DAC16xS055). The DAC161S055 has only a single

channel — Channel 0.

NOTE

DATA WRITING and REGISTER READING instructions encode the channel address as a binary triplet (A2,A1,A0) as the

last three LSBs of the command byte. DAC CONFIGURATION instructions encode the channel selection by a bit set in the

data bytes. For example, when executing the LDAC instruction a payload of {0100 0001} in the least significant byte of the

instruction indicates channels 6 and 0 are targeted.

MNEMONIC Command Byte[7:0] DATA[15:8] DATA [7:0] Description DEFAULT

DAC Configuration

NOP 0 0 0 0 0 0 0 0 xxxx xxxx xxxx xxxx No Operation

CLR 0 0 0 0 0 0 0 1 xxxx xxxx xxxx xxxx Clear internal registers, return to Power-Up

default state

LDAC 0 0 0 1 1 0 0 0 xxxx xxxx CHANNEL[7:0] Software LOAD DAC. A '1' causes data stored in

the specified channel's PREREG to be transferred

to DACREG and the output updated.

SWB 0 0 1 0 1 0 0 0 xxxx xxxx CHANNEL[7:0] Set WRITE BLOCK or WRITE THROUGH for the 00FFh

selected channels.

0: WRITE THROUGH

1: WRITE BLOCK

PD 0 0 1 1 0 0 0 0 CHANNEL[7:0] CHANNEL[7:0] Sets SEL_10K or SEL_HIZ. Upper 8 bits PD Hi-Z; 0000h

Lower 8-bits PD 10K; if both are 1's; PD -> 10K

1: Upper 8 bits: SEL_HIZ

1: Lower 8 bits: SEL_10K

1: Both upper and lower: SEL_10K

Data Writing

WR 0 0 0 0 1 A2 A1 A0 DACDATA[15:8] DACDATA[7:0] Write to specified channel. WRITE BLOCK or

WRITE TRHOUGH setting controls destination

WRUP 0 0 0 1 0 A2 A1 A0 DACDATA[15:8] DACDATA[7:0] Update specified channel's DACREG and

PREREG regardless of WRITE BLOCK or WRITE

THROUGH setting.

WRAL 0 0 1 0 0 0 0 0 DACDATA[15:8] DACDATA[7:0] Update all channel's DACREG and PREREG

regardless of WRITE BLOCK or WRITE

THROUGH setting.

RDDO 1 0 0 0 1 A2 A1 A0 DACDATA[15:8] DACDATA[7:0] Read PREREG register.

Product Folder Links: DAC161S055