Datasheet

DAC161S055
SNAS503B –NOVEMBER 2010–REVISED JANUARY 2012 www.ti.com
INTERNAL REGISTERS
There are 3 registers that are accessible to the user. The data registers (PREREG and DACREG) are both
readable and writable from the command set. The CONFIG register is only readable from the command set. Bits
in the CONFIG register are set by the commands detailed in Section INSTRUCTION SET.
PREREG: DAC Preload Data Register(16Bits)
R/W R/W R/W R/W R/W R/W R/W R/W
MSB PRD15 PRD14 PRD13 PRD12 PRD11 PRD10 PRD9 PRD8
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
R/W R/W R/W R/W R/W R/W R/W R/W
LSB PRD7 PRD6 PRD5 PRD4 PRD3 PRD2 PRD1 PRD0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit15–0: 16 bit data word to be converted. Bit 15 has a weight of 1/2*Vref. Bit 0 has a weight of Vref/2
16
.
DACREG: DAC Output Data Register(16Bits)
R/W R/W R/W R/W R/W R/W R/W R/W
MSB IND15 IND14 IND13 IND12 IND11 IND10 IND9 IND8
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
R/W R/W R/W R/W R/W R/W R/W R/W
LSB IND7 IND6 IND5 IND4 IND3 IND2 IND1 IND0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit15–0: 16 bit data word to be converted. Bit 15 has a weight of 1/2*Vref. Bit 0 has a weight of Vref/2
16
.
CONFIG: DAC Configuration Reporting Register (8 Bits)
R/W R/W R/W R/W R/W R/W R/W R/W
LSB IND7 IND6 IND5 IND4 IND3 IND2 IND1 IND0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7–3: Reserved. Read value is undefined and should be discarded.
Bit2: SWB: Set Write Block bit
0: Channel is in WRITE THROUGH mode.
1: Channel is in WRITE BLOCK mode.
Bit1: 0: Channel is either active or SEL_HIZ is set.
1: Channel is powered down and output is terminated by a 10K resistor to GND.
Bit0: 0: Channel is either active or SEL_10K is set.
1: Channel is powered down and output is in high impedance state.
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