Datasheet

DATA (3)MOSI
SYNC
DATA (1)
DATA (2)
72 Clock Cycles
SDI
CSB
SDO
SCLK
DAC161S055
SDI
CSB
SDO
SCLK
DAC161S055
SDI
CSB
SDO
SCLK
DAC161S055
MOSI
MISO
CLK
SYNC
SPI/QSPI
MICROWIRE
MASTER
(1) (2) (3)
DAC161S055
SNAS503B –NOVEMBER 2010–REVISED JANUARY 2012 www.ti.com
A sample of SPI data transfer appropriate for a 3 DAC Daisy Chain is shown in the figure below.
POWER-UP DEFAULT OUTPUT
It is possible to power up the DAC with the output either at GND or midscale. This functionality is achieved by
connecting the MZB pin either to GND or to VA (note, the MZB pin is referenced to VA, not VDDIO). Usually this
function is hardwired in the application, but can also be controlled by a GPIO pin of the µC. To power up with
output at zero, tie the MZB pin low. To power up with output at midscale, tie MZB high. The MZB pin is level
sensitive.
CHANGING DAC OUTPUT
There are multiple different ways to affect the DAC output. The CONFIG register can be changed so that a write
to the PREREG is seen instantly at the output. The LDAC function or LDACB pin updates the output instantly.
Finally, the type of write command (WRUP, WRAL, WR) can affect if the output updates instantly or not.
Write-Through and Write-Block Modes
Using the SWB bit of the CONFIG register, the user can set the part in WRITE-BLOCK or WRITE-THROUGH
mode.
If the DAC channel is configured in the WRITE-BLOCK mode (SWB=0, default), the DAC input DATA is held in
the PREREG until the controller forces the transfer of DATA from PREREG to DACREG register. Only DATA in
DACREG register is converted to the equivalent analog output. The transfer from PREREG into DACREG can be
forced by both software and hardware LDAC commands. The Data Writing commands WRUP and WRAL update
both PREREG and DACREG at the same time regardless of the channel mode. WRITE-BLOCK mode is used in
multi device or multi channel applications. A user can preload all DAC channels with desired data, in multiple SPI
transactions, and then issue a single software LDAC command (or toggle the LDACB pin) to simultaneously
update all analog outputs.
If the DAC channel is configured in WRITE-THROUGH mode (SWB=1) the controller updates both PREREG and
DACREG registers simultaneously. Therefore in WRITE-THROUGH mode the channel output is updated as soon
as the SPI transfer is completed i.e. upon the rising edge of CSB.
LDAC Function
The LDACB (Load DAC) pin provides a easy way to synchronize several DACs and update the output without
any SPI latency. If the LDACB is asserted low, the content of the PREREG register is instantaneously moved
into the DACREG register. The LDACB pin is level sensitive. If the LDACB pin is held low continuously, the DAC
output will update as soon as the CSB pin goes high.
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