Datasheet

RDDO/RDCO/RDIN
'RQ¶W&DUH
16 bits
Next Command
Next Data
Prior Command Prior Data
RDDO/RDCO/RDIN REG DATA
HiZ
HiZHiZ
CSB
SDI
SDO
8 bits
16 bits
8 bits
16 bits
8 bits
16 bits
8 bits
CSB
SDI
COMMAND
8 bits
DATA
16 bits
DAC161S055
www.ti.com SNAS503B –NOVEMBER 2010–REVISED JANUARY 2012
The acquired data is shifted into an internal 24 bit shift register (MSB first) which is configured as a 24 bit deep
FIFO. As the data is being shifted into the FIFO via the SDI pin, the prior contents of the register are being
shifted out through the SDO output. While CSB is high, SDO is in a high-Z state. At the falling edge of CSB, SDO
presents the MSB of the data present in the shift register. SDO is updated on every subsequent falling edge of
SCLK (note — the first SDO transition will happen on the first falling edge AFTER the first rising edge of SCLK
when CSB is low).
The 24 bits of data contained in the FIFO are interpreted as an 8 bit COMMAND word followed by 16 bits of
DATA. The general format of the 24 bit data stream is shown below. The full Instruction Set is tabulated in
Section INSTRUCTION SET.
1.4.1 SPI Write
SPI write operation is the simplest transaction available to the user. There is no handshaking between master
and the slave (DAC161S055), and the master is the source of all signals required for communication: SCLK,
CSB, SDI. The format of the data transfer is described in the section 1.4. The user instruction set is shown in
Section INSTRUCTION SET.
SPI Read
The read operation requires all 4 wires of the SPI interface: SCLK, SCB, SDI, SDO. The simplest READ
operation occurs automatically during any valid transaction on the SPI bus since SDO pin of DAC161S055
always shifts out the contents of the internal FIFO. Therefore the user can verify the data being shifted in to the
FIFO by initiating another transaction and acquiring data at SDO. This allows for verification of the FIFO contents
only.
The 3 internal registers (PREREG, DACREG, CONFIG) can be accessed by the user through the Register Read
commands: RDDO, RDIN, RDCO respectively (see Section INSTRUCTION SET). These operations require 2
SPI transaction to recover the register data. The first transaction shifts in the Register Read command; an 8 bit
command byte followed by 16 bit “dummy” data. The Register Read command will cause the transfer of contents
of the internal register into the FIFO. The second transaction will shift out the FIFO contents; an 8 bit command
byte (which is a copy of previous transaction) followed by the register data. The Register Read operation is
shown in the figure below.
SPI Daisy Chain
It is possible to control multiple DACs or other SPI devices with a single master equipped with one SPI interface.
This is accomplished by connecting the DACs in a Daisy Chain. The scheme is depicted in the figure below. An
arbitrary length of the chain and an arbitrary number of control bits for other devices in the chain is possible since
individual DAC devices do not count the data bits shifted in. Instead, they wait to decode the contents of their
respective shift registers until CSB is raised high.
A typical bus cycle for this scheme is initiated by the falling CSB. After the 24 SCLK cycles new data starts to
appear at the SDO pin of the first device in the chain, and starts shifting into the second device. After 72 SCLK
cycles following the falling CSB edge, all three devices in this example will contain new data in their input shift
registers. Raising CSB will begin the process of decoding data in each DAC. When in the Daisy Chain the full
READ and WRITE capability of every device is maintained.
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