Datasheet

CSB
SCLK
SDI
SDO
HiZ
HiZ
1
2 2343 24
D23 D20
D0
D21D22
D1
Preceeding Transfer Data
DAC161S055
SNAS503B –NOVEMBER 2010–REVISED JANUARY 2012 www.ti.com
FUNCTIONAL DESCRIPTION
DAC ARCHITECTURE OVERVIEW
The DAC161S055 uses a resistor array to convert the input code to an analog signal, which in turn is buffered by
the rail-to-rail output amplifier. The resistor array is factory trimmed to achieve 16-bit accuracy.
An SPI interface shifts the input codes into the device. The acquired input code is stored in the PREREG
register. After the input code is transferred to the DACREG register it affects the state of the resistor array and
the output level of the DAC. The transfer can be initiated by the type of write command used, by a software
LDAC command or by the state of the LDACB pin.
The user can control the power up state of the output using the MZB pin and the power down state of the output
using the CONFIG register. Additionally, there are external pins and CONFIG register bits that also control
clearing the DAC.
NOTE
Although the DAC161S055 is a single channel device, the instruction set is for
multichannel DACs. The user must address channel 0 (A2,A1,A0={000}).
OUTPUT AMPLIFIER
The output buffer amplifier is a rail to rail type which buffers the signal produced by the resistor array and drives
the external load. All amplifiers, including rail to rail amplifiers, exhibit a loss of linearity as the output nears the
power rails (in this case GND and V
A
). Thus the linearity of the part is specified over less than the full output
range. The user can program the CONFIG register to power down the amplifier and either place it in the high
impedance state (HiZ), or have the output terminated by an internal 10 kΩ pull-down resistor.
REFERENCE
An external reference source is required to produce an output. The reference input is not internally buffered and
presents a resistive load to the external source. Loading presented by the VREF pin varies by about 12.5%
depending on the input code. Thus a low impedance reference should be used for best results.
SERIAL INTERFACE
The 4-wire interface is compatible with SPI, QSPI and MICROWIRE, as well as most DSPs. See the TIMING
DIAGRAMS for timing information about the read and write sequences. The serial interface is the four signals
CSB, SCLK, SDI and SDO.
A bus transaction is initiated by the falling edge of the CSB. Once CSB is low, the input data is sampled at the
SDI pin by the rising edge of the SCLK. The output data is put out on the SDO pin on the falling edge of SCLK.
At least 24 SCLK cycles are required for a valid transfer to occur. If CSB is raised before 24th rising edge of the
SCLK, the transfer is aborted. If the CSB is held low after the 24th falling edge of the SCLK, the data will
continue to flow through the FIFO and out the SDO pin. Once CSB transitions high, the internal controller will
decode the most recent 24 bits that were received before the rising edge of CSB. The DAC will then change
state depending on the instruction sent and the state of the LDACB pin.
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