Datasheet

0V
VDD
V
O
V
IH
0V
V
S
T
PEAK
Dominant response
Response due to
parasitics
DELAY=TD
C
P
C
DIN
A
DAC161P997
Transformer
Model
B
DIN
DBACK
Tx
V
P
+
-
V
S
+
-
R
O
V
O
+
-
Use IDEAL
device models
DAC161P997
www.ti.com SNAS515E –JULY 2011–REVISED OCTOBER 2013
Table 3. Transformer Model Parameters' Legend
Parameter Description
L
M
Magnetizing inductance, in Data Sheets shown as OCL (open circuit inductance)
L
LP/S
Leakage inductance of the primary (secondary) winding
Winding capacitance. Dominated by the CWW (winding to winding) component. Here it is assumed
C
WP/S
that CWS=CWP=½CWW
R
P/S
Winding resistance
The circuit behavior will be dominated by the DC blocking capacitance C
P
and the magnetizing inductance L
M
. In
the example circuit shown in Figure 32 the rising edge of VO ultimately results in an impulse at the input DIN,
see Figure 33. Once voltage at DIN is above VIH of the A buffer, the A buffer will change its state. However, the
latch will acquire a new state only if the voltage at DIN persists above VIH for T
PEAK
> TD.
The parasitic elements in the transformer model: L
LS
, L
SP
, C
WS
, C
WP
may result in the oscillating component
superimposed on the dominant impulse response waveform shown in Figure 33. The oscillation should be
controlled so that the condition T
PEAK
> TD is maintained. The typical method for controlling this parasitic
oscillation is to insert a damping element into the signal path. A small resistance in series with transformer
winding is such damping element. The typical application example in Application Circuit Examples illustrates this.
The delay around the SWIF input latch, from DIN to DBACK, TD is specified in ELECTRICAL
CHARACTERISTICS.
Figure 32. NRZ Waveform Transmission and Recovery Circuit Model
Figure 33. SWIF Link Circuit Response to Step Input
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