Datasheet

pri_tx / pri_rx
pri_tx_en_n
1:1
DAC161P997
(Slave)
a
d
c
b
DIN
DBACK
ACKB
Master
COMD
74LVC125
pri_tx / pri_rx
pri_tx_en_n
74LVC125
1:1
DAC161P997
(Slave)
a
d
c
b
DIN
DBACK
ACKB
Master
COMD
DAC161P997
SNAS515E –JULY 2011–REVISED OCTOBER 2013 www.ti.com
SWIF Implementation Examples
An example of implementation of the SWIF data link is shown in the figure below. This implementation uses the
components already present in the systems employing the standard methods for PWM signal transmission over
an isolation boundary. In this example Master uses 2 digital I/Os:
• One bidirectional port for transmitting encoded data to, and receiving the acknowledge signal from the slave –
pri_tx/pri_rx.
• One output sourcing the pri_tx_en_n signal that governs the direction of the data flow over the SWIF link.
While transmitting, Master drives the pri_tx_en_n LOW and sources data stream onto the pri_tx. The circuit path
is through buffer ‘a’, transformer primary winding, DC blocking capacitor to GND.
While receiving, Master drives the pri_tx_en_n HIGH and ‘listens’ for acknowledge signal pri_rx. In this mode the
buffers ‘a’ and ‘b’ form the latch around the transformer winding, and buffer ‘c’ floats the DC blocking capacitor.
Figure 25. Typical SWIF implementation
The interface implementation shown in Figure 25 can be expanded or simplified depending on the requirements
of the system and capabilities of the Master controller. A number of other possible implementations are shown in
the figures below.
Figure 26 shows the circuit analogous in its functionality to the circuit in Figure 25 but with fewer active
components. Here instead of disabling ‘b’ buffer during data transmission, its output impedance is increased to
the point where its drive is significant only during the data reception form the Slave.
Figure 26. SWIF Link with Simplified Control
Figure 27 shows the SWIF link circuit when the Master does not have a bidirectional I/O available. The Master
output driving pri_tx is split away from the Master receiving pri_rx input by using a buffer ‘d’, until now unused, on
74LVC125.
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