Datasheet
DAC161P997
www.ti.com
SNAS515E –JULY 2011–REVISED OCTOBER 2013
REGISTER SET
LCK
Address=0x00; Default=0x00
Bit Field Name Description
0x95 - registers unlocked
0x** - any value written locks registers
7:0
A register lock prevents inadvertent changes to the configuration. The DAC output cannot be
updated while software configuration registers are unlocked.
CONFIG1
Address=0x01; Default=0x08
Bit Field Name Description
7:5 RESERVED. Always write 0.
0b00 - NOP
0b01 - set error
0b10 - clear error
0b11 - NOP
4:3 SERR
Sets or clears the error condition. At power-on the error is set. Error is also cleared after
reception of valid SWIF frame. These bits are self clearing.
This functionality can be used for diagnostic purposes, e.g. Master can use SERR to force
I
LOOP
into an error band, and then return it to previously held output level.
2:1 RESERVED. Always write 0.
0 - NOP
0 RST
1- same as power-on reset. Once device is reset to default state the bit clears automatically
CONFIG2
Address=0x02; Default=0x1F
Bit Field Name Description
7:5 RESERVED. Always write 0.
Set to enable ACK
4 ACK_EN When enabled, an acknowledgement is indicated on the serial interface upon detection of
each valid frame. See Frame Format.
3 FRAME Set to enable framing error reporting. See table in Error Detection and Reporting.
2 PARITY Set to enable parity error reporting. See table in Error Detection and Reporting.
1 CHANNEL Set to enable channel-inactive reporting. See table in Error Detection and Reporting.
0 LOOP Set to enable loop error reporting. See table in Error Detection and Reporting.
CONFIG3
Address=0x03; Default=0x08
Bit Field Name Description
7:4 RESERVED. Always write 0.
0 <= RX_ERR_CNT ≤ 15 Threshold = 1 + RX_ERR_CNT
The slave enters the error state once ‘Threshold’ number of consecutive FRAME or PARITY
3:0 RX_ERR_CNT
errors are counted. The threshold is programmable to prevent occasional errors from being
reported. See table in Error Detection and Reporting.
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