Datasheet

1 10 100 1k 10k 100k 1M
0
20
40
60
80
100
120
PSRR (dB)
FREQUENCY (Hz)
C1=C2=C3=1nF
C1=C2=C3=2.2nF
C1=C2=C3=10nF
C1=C2=C3=100nF
-40 -20 0 20 40 60 80 100 120
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
INL (A)
TEMPERATURE (°C)
Min INL
Max INL
1 10 100 1k 10k 100k 1M
0
20
40
60
80
100
120
PSRR (dB)
FREQUENCY (Hz)
C1=C2=C3=1nF
C1=C2=C3=2.2nF
C1=C2=C3=10nF
C1=C2=C3=100nF
1 10 100 1k 10k 100k
1
10
100
1k
10k
100k
1M
SETTLING TIME (s)
INPUT CODE STEP (lsb)
C1=C2=C3=2.2nF
HART Adaptation
C1=C2=C3=1nF
0 4 8 12 16 20 24
0
50
100
150
200
250
300
TOTAL SUPLLY CURRENT (A)
OUTPUT CURRENT (mA)
VA=VD=2.7V
VA=VD=3.0V
VA=VD=3.3V
VA=VD=3.6V
DAC161P997
SNAS515E –JULY 2011–REVISED OCTOBER 2013 www.ti.com
Unless otherwise noted, data presented here was collected under these conditions V
A
= V
D
= 3.3V, T
A
= 25°C, external
bipolar transistor: 2N3904, R
E
= 22Ω, C
1
= C
2
= C
3
= 2.2 nF.
Settling Time vs Input Step Size Supply Current vs I
LOOP
Figure 8. Figure 9.
Output Linearity vs Temperature PSRR: I
LOOP
=4mA
Figure 10. Figure 11.
PSRR: I
LOOP
=20mA
Figure 12.
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