Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DAC 16 Bit LLP 16 EP

DAC161P997

www.ti.com

SNAS515E –JULY 2011–REVISED OCTOBER 2013

DAC161P997 Single-Wire 16-bit DAC for 4-20mA Loops

Check for Samples: DAC161P997

FEATURES

DESCRIPTION

The DAC161P997 is a 16- bit ∑Δ digital-to-analog

• 16-bit Linearity

converter (DAC) for transmitting an analog output

• Single-Wire Interface (SWIF), with Handshake

current over an industry standard 4-20 mA current

• Digital Data Transmission (No Loss of Fidelity)

loop. It offers 16-bit accuracy with a low output

current temperature coefficient (29ppm/°C) and

• Pin Programmable Power-Up Condition

excellent long-term output current drift (90 ppmFS)

• Self Adjusting to Input Data Rate

while consuming less than 190µA.

• Loop Error Detection and Rreporting

The data link to the DAC161P997 is a Single Wire

• Programmable Output Current Error Level

Interface (SWIF) which allows sensor data to be

• No External Precision Components

transferred in digital format over an isolation

boundary using a single isolation component. The

• Simple Interface to HART Modulator

DAC161P997’s digital input is compatible with

• Small Package: WQFN-16 (4x4 mm, 0.5 mm

standard isolation transformers and optocouplers.

Pitch)

Error detection and handshaking features within the

SWIF protocol ensure error free communication

APPLICATION

across the isolation boundary. For applications where

isolation is not required, the DAC161P997 interfaces

• Two-Wire, 4-20 mA Current Loop Transmitter

directly to a microcontroller.

• Industrial Process Control

The loop drive of the DAC161P997 interfaces to a

• Actuator Control

HART (Highway Addressable Remote Transducer)

• Factory Automation

modulator, allowing injection of FSK modulated digital

• Building Automation

data into the 4-20mA current loop. This combination

of specifications and features makes the

• Precision Instruments

DAC161P997 ideal for 2- and 4-wire industrial

• Data Acquisition Systems

transmitters.

• Test Systems

The DAC161P997 is available in a 16–lead WQFN

package and is specified over the extended industrial

KEY SPECIFICATIONS

temperature range of -40°C to 105°C.

• Output Current TempCo: 29 ppmFS/°C(Max)

• Long-Term Output Current Drift: 90 ppmFS

(Typ)

• INL: +3.3/−2.1 µA(Max)

• Total Supply Current: 190 µA(Max)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (36 pages)

PAGE 1
DAC161P997 www.ti.com SNAS515E – JULY 2011 – REVISED OCTOBER 2013 DAC161P997 Single-Wire 16-bit DAC for 4-20mA Loops Check for Samples: DAC161P997 FEATURES DESCRIPTION • • • • • • • • • • The DAC161P997 is a 16- bit ∑Δ digital-to-analog converter (DAC) for transmitting an analog output current over an industry standard 4-20 mA current loop.
PAGE 2
DAC161P997 SNAS515E – JULY 2011 – REVISED OCTOBER 2013 www.ti.
PAGE 3
DAC161P997 www.ti.com SNAS515E – JULY 2011 – REVISED OCTOBER 2013 Functional Overview 4-20 mA CURRENT LOOP TRANSMITTER The DAC161P997 is a 16-bit DAC realized as a ∑Δ modulator. The DAC’s output is a current pulse train that is filtered by the on-board low pass RC filter. The final output current is a multiplied copy of the filtered modulator output. This architecture ensures an excellent linearity performance, while minimizing power consumption of the device.
PAGE 4
DAC161P997 SNAS515E – JULY 2011 – REVISED OCTOBER 2013 www.ti.com COMA 1 COMD 2 VA C1 C2 15 14 13 BASE 16 Connection Diagram 12 C3 11 NC DAP=COMA 8 ERRLVL DBACK 7 OUT 6 LOW 9 ACKB 10 4 ERRB 3 5 VD DIN Figure 1.
PAGE 5
DAC161P997 www.ti.com SNAS515E – JULY 2011 – REVISED OCTOBER 2013 PIN DESCRIPTIONS (continued) Name Pin Function ERRB 7 Error flag output open drain, active LOW ESD Protection COMA COMA OUT DAP 9 Loop output current source - Die Attach Pad. For best thermal conductivity and best noise immunity DAP should be soldered to the PCB pad which is connected directly to circuit common node (COMA, COMD) - These devices have limited built-in ESD protection.
PAGE 6
DAC161P997 SNAS515E – JULY 2011 – REVISED OCTOBER 2013 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) (2) (3) −0.3V to 6.0V Supply relative to common (VA, VD to COMA, COMD) Voltage between any 2 pins (4) 6.
PAGE 7
DAC161P997 www.ti.com SNAS515E – JULY 2011 – REVISED OCTOBER 2013 ELECTRICAL CHARACTERISTICS (continued) Unless otherwise noted, these specifications apply for VA = VD = 2.7V to 3.6V, TA = 25°C, external bipolar transistor: 2N3904, RE = 22Ω, C1 = C2 = C3 = 2.2nF. Boldface limits are over the temperature range of −40°C ≤ TA ≤ 105°C unless otherwise noted.
PAGE 8
DAC161P997 SNAS515E – JULY 2011 – REVISED OCTOBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Unless otherwise noted, these specifications apply for VA = VD = 2.7V to 3.6V, TA = 25°C, external bipolar transistor: 2N3904, RE = 22Ω, C1 = C2 = C3 = 2.2nF. Boldface limits are over the temperature range of −40°C ≤ TA ≤ 105°C unless otherwise noted.
PAGE 9
DAC161P997 www.ti.com SNAS515E – JULY 2011 – REVISED OCTOBER 2013 Typical Performance Characteristics Unless otherwise noted, data presented here was collected under these conditions VA = VD = 3.3V, TA = 25°C, external bipolar transistor: 2N3904, RE = 22Ω, C1 = C2 = C3 = 2.2 nF.
PAGE 10
DAC161P997 SNAS515E – JULY 2011 – REVISED OCTOBER 2013 www.ti.com Unless otherwise noted, data presented here was collected under these conditions VA = VD = 3.3V, TA = 25°C, external bipolar transistor: 2N3904, RE = 22Ω, C1 = C2 = C3 = 2.2 nF. Settling Time vs Input Step Size Supply Current vs ILOOP 300 TOTAL SUPLLY CURRENT ( A) 1M SETTLING TIME ( s) 100k 10k 1k 100 10 C1=C2=C3=2.2nF HART Adaptation C1=C2=C3=1nF 1 1 10 100 1k 10k INPUT CODE STEP (lsb) 250 200 150 VA=VD=2.7V VA=VD=3.0V VA=VD=3.
PAGE 11
DAC161P997 www.ti.com SNAS515E – JULY 2011 – REVISED OCTOBER 2013 REGISTER SET LCK Address=0x00; Default=0x00 Bit Field Name Description 0x95 - registers unlocked 0x** - any value written locks registers A register lock prevents inadvertent changes to the configuration. The DAC output cannot be updated while software configuration registers are unlocked. 7:0 CONFIG1 Address=0x01; Default=0x08 Bit Field Name Description 7:5 RESERVED. Always write 0.
PAGE 12
DAC161P997 SNAS515E – JULY 2011 – REVISED OCTOBER 2013 www.ti.com ERR_LOW Address=0x04; Default=0x24 Bit Field Name Description 8-bit value. If ERRLVL = LOW, the DAC will use the value stored in ERR_LOW register to set the output current sourced from OUT pin when reporting an error condition. The ERR_LOW value is used as the upper byte of the DACCODE, while the lower byte is forced to 0x00. At power up the ERR_LOW defaults to a value which forces IERRL output current. See ELECTRICAL CHARACTERISTICS.
PAGE 13
DAC161P997 www.ti.com SNAS515E – JULY 2011 – REVISED OCTOBER 2013 APPLICATION INFORMATION 16-BIT DAC AND LOOP DRIVE DC Characteristics The DAC converts the 16-bit input code in the DACCODE register to an equivalent current output. The ∑Δ DAC output is a current pulse which is then filtered by a 3rd order RC low-pass filter and boosted to produce the loop current ILOOP at the device OUT pin.
PAGE 14
DAC161P997 SNAS515E – JULY 2011 – REVISED OCTOBER 2013 www.ti.com LOOP+ VD + - VLOCAL IAUX VA DAC + BASE ILOOP IA - ID + IDAC IE RE COMA R1 = 80k R2 = 40 I2 OUT DAC161P997 LOOP- Figure 14. Self-Powered Transmitter DC Input-Output Transfer Function The output current sourced by the OUT pin of the device is expressed by: (2) The valid DACCODE range is the full 16-bit code space (0x0000 to 0xFFFF), which results in the IDAC range of 0 to approximately 12 μA.
PAGE 15
DAC161P997 www.ti.com SNAS515E – JULY 2011 – REVISED OCTOBER 2013 Loop Interface The DAC161P997 cannot directly interface to the typical 4 - 20 mA loop due to the excessive loop supply voltage. The loop interface has to provide the means of stepping down the LOOP Supply down to 3.6V.
PAGE 16
DAC161P997 SNAS515E – JULY 2011 – REVISED OCTOBER 2013 www.ti.com (3) LOOP+ ILOOP A(s)Gmve A(s)Gm + + IAUX - ro ve - IDAC R1 R2 ILOOP LOOP- Figure 17.
PAGE 17
DAC161P997 www.ti.com SNAS515E – JULY 2011 – REVISED OCTOBER 2013 Step Response The transient input-output characteristics of the DAC161P997 are dominated by the response of the RC filter at the output of the ∑Δ DAC. Settling times due to step input are shown in Typical Performance Characteristics.
PAGE 18
DAC161P997 SNAS515E – JULY 2011 – REVISED OCTOBER 2013 www.ti.com Noise and Ripple The output of the DAC is a current pulse train. The transition density varies throughout the DAC input code range (ILOOP range). At the extremes of the code range, the transition density is the lowest which results in low frequency components of the DAC output passing through the RC filter.
PAGE 19
DAC161P997 www.ti.com SNAS515E – JULY 2011 – REVISED OCTOBER 2013 SINGLE-WIRE INTERFACE (SWIF) SWIF provides flexible and easy to implement digital data link between the Master (transmitter) and the Slave (receiver). The Master encodes the digital data into a square (NRZ) CMOS level waveform which can be generated using common microcontroller resources. The Slave (DAC161P997) translates the waveform back into a bit stream which is then interpreted as the output current update or configuration data.
PAGE 20
DAC161P997 SNAS515E – JULY 2011 – REVISED OCTOBER 2013 www.ti.com Inter-Frame Period The fastest DAC update rate is achieved when Master sends the valid frames back to back, Continuous Mode, at the fastest Baud rate. This, however, results in the least power efficient implementation. Frame Frame Frame SWIF is designed to operate in the Burst Mode as well, where the valid frames are separated by the inter-frame periods that do not carry any data.
PAGE 21
DAC161P997 www.ti.com SNAS515E – JULY 2011 – REVISED OCTOBER 2013 Table 1.
PAGE 22
DAC161P997 SNAS515E – JULY 2011 – REVISED OCTOBER 2013 www.ti.com DBACK DAC161P997 B C 8k to SWIF decoder DIN A ACKB COMD Figure 21. SWIF Front End Transformer Coupled Interface - Data Flow to the DAC In systems requiring galvanic isolation between the transmitter (micro-controller) and the receiver, the commonly used coupling element is a pulse transformer. Transformer passes only the AC components of the square input waveform resulting in an impulse train across the secondary winding.
PAGE 23
DAC161P997 www.ti.com SNAS515E – JULY 2011 – REVISED OCTOBER 2013 Transformer Coupled Interface - Acknowledge Pulse Since the transformer is a symmetrical device (particularly one with 1:1 winding ratio), it is simple to reverse the data flow through it. Figure 23 shows the SWIF interface circuit during the transmission of the Acknowledge pulse from the DAC161P997 on the secondary side back to the micro-controller on the primary side.
PAGE 24
DAC161P997 SNAS515E – JULY 2011 – REVISED OCTOBER 2013 www.ti.com SWIF Implementation Examples An example of implementation of the SWIF data link is shown in the figure below. This implementation uses the components already present in the systems employing the standard methods for PWM signal transmission over an isolation boundary. In this example Master uses 2 digital I/Os: • One bidirectional port for transmitting encoded data to, and receiving the acknowledge signal from the slave – pri_tx/pri_rx.
PAGE 25
DAC161P997 www.ti.com SNAS515E – JULY 2011 – REVISED OCTOBER 2013 DBACK 1:1 a pri_rx DIN b Master ACKB c pri_tx_en_n pri_tx d DAC161P997 (Slave) 74LVC125 COMD Figure 27. Master without Bidirectional I/O Figure 28 shows the trivial circuit realization of the SWIF link in simplex mode, unidirectional data flow. pri_tx 1:1 DBACK DIN Master ACKB DAC161P997 (Slave) COMD Figure 28. SWIF without Acknowledge Capability Figure 29 shows the DC coupled SWIF link realization.
PAGE 26
DAC161P997 SNAS515E – JULY 2011 – REVISED OCTOBER 2013 www.ti.com The SWIF link realization using opto-couplers (opto-isolators) is shown in Figure 30. Points of note here are: the opto-couplers invert the SWIF symbol waveform, and there is increased power consumption due to the relatively large currents required to turn on the internal diodes and standing current in the pull-up resistors. DBACK pri_rx_b Master DIN pri_tx_b ACKB DAC161P997 (Slave) COMD Figure 30.
PAGE 27
DAC161P997 www.ti.com SNAS515E – JULY 2011 – REVISED OCTOBER 2013 Table 3. Transformer Model Parameters' Legend Parameter Description LM Magnetizing inductance, in Data Sheets shown as OCL (open circuit inductance) LLP/S Leakage inductance of the primary (secondary) winding CWP/S Winding capacitance. Dominated by the CWW (winding to winding) component.
PAGE 28
DAC161P997 SNAS515E – JULY 2011 – REVISED OCTOBER 2013 www.ti.com ERROR DETECTION AND REPORTING The user can modify the CONFIG2:(LOOP | CHANNEL | PARITY | FRAME) bits to mask or enable the reporting of any of the detectable fault conditions. The DAC161P997 reports errors by asserting the ERRB signal, and by setting the current sourced by OUT to a value dictated by the state at ERRLVL pin and the contents of the ERR_HIGH and ERR_LOW registers.
PAGE 29
DAC161P997 www.ti.com SNAS515E – JULY 2011 – REVISED OCTOBER 2013 REVISION HISTORY Changes from Revision C (March 2013) to Revision D • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 28 Changes from Revision D (March, 2013) to Revision E • Page Changed application circuit ....................................................................................................................
PAGE 30
PACKAGE OPTION ADDENDUM www.ti.
PAGE 31
PACKAGE MATERIALS INFORMATION www.ti.com 7-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DAC161P997CISQ/NOPB WQFN DAC161P997CISQX/NOP B WQFN SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant RGH 16 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 RGH 16 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.
PAGE 32
PACKAGE MATERIALS INFORMATION www.ti.com 7-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC161P997CISQ/NOPB WQFN RGH 16 1000 213.0 191.0 55.0 WQFN RGH 16 4500 367.0 367.0 35.
PAGE 33
PACKAGE OUTLINE RGH0016A WQFN - 0.8 mm max height SCALE 3.500 WQFN 4.1 3.9 B A PIN 1 INDEX AREA 0.5 0.3 0.3 0.2 4.1 3.9 DETAIL OPTIONAL TERMINAL TYPICAL C 0.8 MAX SEATING PLANE (0.1) TYP 2.6 0.1 5 8 SEE TERMINAL DETAIL 12X 0.5 4 9 4X 1.5 1 12 16X PIN 1 ID (OPTIONAL) 13 16 16X 0.3 0.2 0.1 0.05 C A C B 0.5 0.3 4214978/A 10/2013 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2.
PAGE 34
EXAMPLE BOARD LAYOUT RGH0016A WQFN - 0.8 mm max height WQFN ( 2.6) SYMM 16 13 SEE DETAILS 16X (0.6) 16X (0.25) 1 12 (0.25) TYP SYMM (3.8) (1) 9 4 12X (0.5) 5X ( 0.2) VIA 8 5 (1) (3.8) LAND PATTERN EXAMPLE SCALE:15X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND METAL SOLDER MASK OPENING METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214978/A 10/2013 NOTES: (continued) 4.
PAGE 35
EXAMPLE STENCIL DESIGN RGH0016A WQFN - 0.8 mm max height WQFN SYMM (0.675) METAL TYP 13 16 16X (0.6) 16X (0.25) 12 1 (0.25) TYP (0.675) SYMM (3.8) 12X (0.5) 9 4 8 5 4X (1.15) (3.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 78% PRINTED SOLDER COVERAGE BY AREA SCALE:15X 4214978/A 10/2013 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.
PAGE 36
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.